Re: [PATCH v6 3/4] riscv: dts: starfive: jh7110: Add PWM node and pins configuration

Emil Renner Berthing
2023-10-25T13:45:50Z

William Qiu wrote:
> Add OpenCores PWM controller node and add PWM pins configuration
> on VisionFive 2 board.
>
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> .../jh7110-starfive-visionfive-2.dtsi | 22 +++++++++++++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 ++++++++
> 2 files changed, 31 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index 12ebe9792356..63d16a6a4e12 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -268,6 +268,12 @@ reserved-data@600000 {
> };
> };
>
> +&pwm {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm_pins>;
> + status = "okay";
> +};
> +

Hi William,

I just noticed this node reference is out of order. The references should be
sorted alphabetically.

/Emil

> &spi0 {
> pinctrl-names = "default";
> pinctrl-0 = <&spi0_pins>;
> @@ -402,6 +408,22 @@ GPOEN_SYS_SDIO1_DATA3,
> };
> };
>
> + pwm_pins: pwm-0 {
> + pwm-pins {
> + pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
> + GPOEN_SYS_PWM0_CHANNEL0,
> + GPI_NONE)>,
> + <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
> + GPOEN_SYS_PWM0_CHANNEL1,
> + GPI_NONE)>;
> + bias-disable;
> + drive-strength = <12>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + };
> +
> spi0_pins: spi0-0 {
> mosi-pins {
> pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index e85464c328d0..4024165d4538 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -736,6 +736,15 @@ spi6: spi@120a0000 {
> status = "disabled";
> };
>
> + pwm: pwm@120d0000 {
> + compatible = "starfive,jh71x0-pwm";
> + reg = <0x0 0x120d0000 0x0 0x10000>;
> + clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
> + resets = <&syscrg JH7110_SYSRST_PWM_APB>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> sfctemp: temperature-sensor@120e0000 {
> compatible = "starfive,jh7110-temp";
> reg = <0x0 0x120e0000 0x0 0x10000>;
> --
> 2.34.1
>