From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5D9440862F for ; Tue, 21 Jul 2026 06:23:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.174 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784615013; cv=none; b=e5puuzGvUbEBBgRX9JuAxwzizfQ5Cf3jWzz4O/cHVRDNdiUNHjGgaGaQtZxxsYNrmVFlQ9S3LLNZWeCrkO9soAN2KCBhSBOuz/651ZpSOfYS03ncw98eaC1Aqni43TWmJGW9lKFlSFGyQMx7gnuArYq4XDs+ekIr9mtjNkKNWI4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784615013; c=relaxed/simple; bh=e6kzC03SPcE1puAeEyRx6tDFOav6awc3FKAn0vlS+Js=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=k7Fn0G3ukoZvrkgUxr6HcrDehg1Zx1vmGJPsTYLYWQq0VP85cHZOv/HTYFhKWru8CR1RrdvF6OeB63g8Y2Jp2kEvKurSKQhJ+K35y1L1CKrhWaGCsrFsSjS36d3oWgKxw2a6Dr60A8dJhcs9DrEmj9su24PGQMZyy1JUZ8c+/7Y= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=mwGr7p7r; arc=none smtp.client-ip=209.85.210.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mwGr7p7r" Received: by mail-pf1-f174.google.com with SMTP id d2e1a72fcca58-8487088510aso11038046b3a.0 for ; Mon, 20 Jul 2026 23:23:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784615011; x=1785219811; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=xYDLN0SdG2S2TMSfDca2PEVtas/kjDMgdSeF774LdcY=; b=mwGr7p7rjBOhTi2CgTwgmThV9aXeYPqCZAVl6CHI42nRhhir/3g9gVpcmVAsz4eopR dEZLWgVzJrOReNSQUnkalqqophU670HCryQgsy5reWsPOB073K/X9ndQIie6PVcusZnv viOmfZDEQg0fO8CRwtAipluCck1ohH8e8F1OHJ4YEdrCbjdRmge3N5G0/UoNF+DwbTp+ N31FUhMY7xnY3ZTpKF1TNKRAjynVse9F3e0FlAtgHu3gauB2lVZEDP9wYPHvbxTSiscr pIOcEk2L2M2tlHWNFat6XyPT8RMOcboX1EyZWiiQF9lwl597Wz0VLtqZTvr/T8bgzUKI Xlcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784615011; x=1785219811; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=xYDLN0SdG2S2TMSfDca2PEVtas/kjDMgdSeF774LdcY=; b=JG/yLFy0YISj+jS0ern1Vaho+P/I1cjK5qm1zXnJG6CsXD9MoOayFJSjKm3gt0rWB6 IP4ZWr6WEE4cTcnbv49v5xHTYkG/A37jcrNIO2dqK5F/n6zujpoBJ7r5eMILODEmAQaH IBnHo81MOp/yDMrEVBIioLnFhXVCUxE5TQz34FV3gV9aJEHR/3WKLyNjXiMUzQSNWQk4 bGUOHyym3OFQgbhOvYXw6yu5JQAegJnjFyNX2pBBA7ypAMbrIA0zu5HMTSM4eU5WdFro JW7JJ/6P9vbUux8zxf8e5VQuaZJ7KHiwiO7tr+DD7PUCLcU8B062PS3bGWpSUr84+1/1 UX+A== X-Forwarded-Encrypted: i=1; AHgh+RrO+eemWwFXc8b09h6JSou0hxr2xXRkWHT6s+obtTCXB7g7GGEZQrb20qUKaGjuh3LUniVqvm9FBCA=@vger.kernel.org X-Gm-Message-State: AOJu0YzNC1wupvvl3/7Qcg0iv6QX9W7EhCxlkLvttA75d2Wr5CCYVvY7 82pdtbHvDEjpOwZ6eeUMDN4w4+ALfeFWv6cQH4t2yrPhEIPgVoHRXqmw X-Gm-Gg: AR+sD13dHXEu5tIl1f7lRGa5pa4PcQTVJPQd1SNGlwYCKEdrcDPkmK6ICPuOkw+5hld SI08tl3ls93KUsFx6hmfJZDoTUauPetA4xWqdc/4EyyGwngYwItJZfCR9aPpJhmBJsiHENMKm2E DgoLVIxsfCt5no12Tasd7wib8X2rHYhpiTFJWnjPnSNwJoSkiy0wfciiB3afLScn8y7bhBMLGYn H6slxydJQm1f3xGPjayGcr+hfN35ru8Rgh97gJ9XNf8IgBi8rVQrSFxz8EEPU4zTlOJ7sDz13NS Cfd3yAhBMDGWiaukdw7q3QNi0SRFY7wKaNesTOj841e7MBlvM0Ksjv8mu740jpMknob1tHKKugU pbjYsxWgJbn0HUxZg8M9s4FhpZWv0Lwg320Yj8pNmNOOJeDNKH/3EfKuj44azCM0ZAM+bKRoGsW UidDP9rVc+UzPBk/5XjLvvzEh68ajzqhsMI+qMeLQvjjESUF9eEDXUBKebH/dKX+Bx X-Received: by 2002:a05:6a00:2353:b0:848:7443:f2de with SMTP id d2e1a72fcca58-84c292d1534mr16781590b3a.13.1784615010972; Mon, 20 Jul 2026 23:23:30 -0700 (PDT) Received: from localhost.localdomain (60-250-196-139.hinet-ip.hinet.net. [60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84c4b640050sm4020710b3a.45.2026.07.20.23.23.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Jul 2026 23:23:30 -0700 (PDT) From: Chi-Wen Weng To: ukleinek@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com, cwweng.linux@gmail.com Subject: [PATCH v5 2/2] pwm: Add Nuvoton MA35D1 PWM controller support Date: Tue, 21 Jul 2026 14:23:08 +0800 Message-Id: <20260721062308.536947-3-cwweng.linux@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260721062308.536947-1-cwweng.linux@gmail.com> References: <20260721062308.536947-1-cwweng.linux@gmail.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Chi-Wen Weng Add a PWM framework driver for the Nuvoton MA35D1 EPWM controller. The controller provides 6 PWM channels and supports up, down and up-down counter types, auto-reload and one-shot counter modes, and independent and complementary output modes. The initial driver supports up-counting, auto-reload and independent output modes. It uses period loading mode and configures the waveform generator to drive the output high at the zero point and low at the compare-up point. In up-counting mode, the counter counts from 0 to PERIOD inclusive. With the selected waveform actions, CMPDAT = 0 generates a 0% duty cycle and CMPDAT > PERIOD generates a 100% duty cycle. Limit the period to 0xffff counter cycles so that PERIOD is at most 0xfffe and CMPDAT = 0xffff remains available for the full-duty case. The clock prescaler is shared by each pair of PWM channels. Preserve its existing value and account for CLKPSC + 1 when calculating and reporting the period and duty cycle. Do not modify the controller during probe, preserving PWM outputs that may already have been configured by firmware. Configure only the requested channel from the apply callback. Refuse to change an active complementary pair to independent mode when doing so would disturb the paired output. When disabling a channel, clear its output-enable and counter-enable bits. The output pin is then placed in tri-state by the hardware. Signed-off-by: Chi-Wen Weng --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ma35d1.c | 380 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 391 insertions(+) create mode 100644 drivers/pwm/pwm-ma35d1.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index e8886a9b64d9..d971760b37c6 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -463,6 +463,16 @@ config PWM_LPSS_PLATFORM To compile this driver as a module, choose M here: the module will be called pwm-lpss-platform. +config PWM_MA35D1 + tristate "Nuvoton MA35D1 PWM support" + depends on ARCH_MA35 || COMPILE_TEST + help + Generic PWM framework driver for the Nuvoton MA35D1 PWM + controller, which provides 6 PWM outputs. + + To compile this driver as a module, choose M here: the module + will be called pwm-ma35d1. + config PWM_MAX7360 tristate "MAX7360 PWMs" depends on MFD_MAX7360 diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 5630a521a7cf..7ad761ea27d1 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o obj-$(CONFIG_PWM_LPSS) += pwm-lpss.o obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o +obj-$(CONFIG_PWM_MA35D1) += pwm-ma35d1.o obj-$(CONFIG_PWM_MAX7360) += pwm-max7360.o obj-$(CONFIG_PWM_MC33XS2410) += pwm-mc33xs2410.o obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o diff --git a/drivers/pwm/pwm-ma35d1.c b/drivers/pwm/pwm-ma35d1.c new file mode 100644 index 000000000000..4073cb72054a --- /dev/null +++ b/drivers/pwm/pwm-ma35d1.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for the Nuvoton MA35D1 PWM controller + * + * Copyright (C) 2026 Nuvoton Corporation + * Chi-Wen Weng + * + * Reference Manual: + * https://www.nuvoton.com/resource-download.jsp?tp_GUID=DA05-MA35D16 + * + * Limitations: + * - The hardware supports 6 PWM channels. + * - The hardware supports up, down and up-down counter types. This driver + * supports up-counting mode only. + * - The hardware supports auto-reload and one-shot counter modes. This driver + * supports auto-reload mode only. + * - The hardware supports independent and complementary output modes. This + * driver supports independent mode only. If a channel pair is already active + * in complementary mode, applying a new state to one channel fails with + * -EBUSY to avoid disturbing the paired output. + * - The hardware supports period, immediate, window and center loading modes. + * This driver supports period loading mode only. + * - The hardware supports programmable waveform actions at zero, period and + * compare points. This driver uses zero point high and compare-up point low + * actions for normal PWM output. + * - In up-counting mode, the counter counts from 0 to PERIOD inclusive. With + * zero point high and compare-up point low actions, CMPDAT = 0 produces 0% + * duty and CMPDAT > PERIOD produces 100% duty. + * - The driver limits the period to 0xffff counter cycles so that CMPDAT can + * be set greater than PERIOD to generate a 100% duty cycle. + * - Period and duty cycle changes are buffered by hardware and take effect at + * the end of the current period. + * - The clock prescaler is shared by each channel pair. The driver preserves + * the current prescaler and accounts for it in period and duty calculations. + * - Polarity and waveform-control changes are applied directly and may cause + * a transient output change if the PWM output is running. + * - When disabled, the output pin is put in tri-state by clearing POENn. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MA35D1_REG_PWM_CTL0 0x00 +#define MA35D1_REG_PWM_CTL1 0x04 +#define MA35D1_REG_PWM_CLKPSC(ch) (0x14 + 4 * ((ch) / 2)) +#define MA35D1_REG_PWM_CNTEN 0x20 +#define MA35D1_REG_PWM_PERIOD(ch) (0x30 + 4 * (ch)) +#define MA35D1_REG_PWM_CMPDAT(ch) (0x50 + 4 * (ch)) +#define MA35D1_REG_PWM_WGCTL0 0xb0 +#define MA35D1_REG_PWM_WGCTL1 0xb4 +#define MA35D1_REG_PWM_POLCTL 0xd4 +#define MA35D1_REG_PWM_POEN 0xd8 + +#define MA35D1_PWM_CTL0_CTRLD(ch) BIT(ch) +#define MA35D1_PWM_CTL0_WINLDEN(ch) BIT(8 + (ch)) +#define MA35D1_PWM_CTL0_IMMLDEN(ch) BIT(16 + (ch)) + +#define MA35D1_PWM_CTL1_CNTTYPE_MASK(ch) (0x3 << (2 * (ch))) +#define MA35D1_PWM_CTL1_CNTMODE_MASK(ch) BIT(16 + (ch)) +#define MA35D1_PWM_CTL1_OUTMODE_MASK(ch) BIT(24 + ((ch) / 2)) + +#define MA35D1_PWM_WGCTL_ACTION_MASK 0x3 +#define MA35D1_PWM_WGCTL_ACTION(ch) \ + (MA35D1_PWM_WGCTL_ACTION_MASK << (2 * (ch))) +#define MA35D1_PWM_WGCTL_ACTION_VAL(ch, action) ((action) << (2 * (ch))) +#define MA35D1_PWM_WGCTL_ACTION_LOW 1 +#define MA35D1_PWM_WGCTL_ACTION_HIGH 2 + +#define MA35D1_PWM_CLKPSC_MASK GENMASK(11, 0) +#define MA35D1_PWM_DATA_MASK GENMASK(15, 0) +#define MA35D1_PWM_MAX_CYCLES 0xffff + +#define MA35D1_PWM_CNTEN_EN(ch) BIT(ch) +#define MA35D1_PWM_POEN_EN(ch) BIT(ch) +#define MA35D1_PWM_POLCTL_INV(ch) BIT(ch) + +#define MA35D1_PWM_NUM_CHANNELS 6 + +struct nuvoton_pwm { + void __iomem *base; + unsigned long clkrate; +}; + +static inline struct nuvoton_pwm *nuvoton_pwm_from_chip(struct pwm_chip *chip) +{ + return pwmchip_get_drvdata(chip); +} + +static inline u32 nuvoton_pwm_readl(struct nuvoton_pwm *nvtpwm, + unsigned int offset) +{ + return readl(nvtpwm->base + offset); +} + +static inline void nuvoton_pwm_writel(struct nuvoton_pwm *nvtpwm, + unsigned int offset, u32 value) +{ + writel(value, nvtpwm->base + offset); +} + +static inline void nuvoton_pwm_rmw(struct nuvoton_pwm *nvtpwm, + unsigned int offset, u32 mask, u32 value) +{ + u32 reg; + + reg = nuvoton_pwm_readl(nvtpwm, offset); + reg &= ~mask; + reg |= value & mask; + nuvoton_pwm_writel(nvtpwm, offset, reg); +} + +static bool nuvoton_pwm_channel_active(struct nuvoton_pwm *nvtpwm, + unsigned int ch) +{ + u32 cnten, poen; + u32 mask = BIT(ch); + + cnten = nuvoton_pwm_readl(nvtpwm, MA35D1_REG_PWM_CNTEN); + poen = nuvoton_pwm_readl(nvtpwm, MA35D1_REG_PWM_POEN); + + return (cnten | poen) & mask; +} + +static u32 nuvoton_pwm_get_prescale(struct nuvoton_pwm *nvtpwm, + unsigned int ch) +{ + return nuvoton_pwm_readl(nvtpwm, MA35D1_REG_PWM_CLKPSC(ch)) & + MA35D1_PWM_CLKPSC_MASK; +} + +static int nuvoton_pwm_config_channel(struct nuvoton_pwm *nvtpwm, + unsigned int ch) +{ + u32 ctl0_mask; + u32 ctl1, ctl1_mask, outmode_mask; + u32 wgctl0_mask, wgctl0_val; + u32 wgctl1_mask, wgctl1_val; + + outmode_mask = MA35D1_PWM_CTL1_OUTMODE_MASK(ch); + ctl1 = nuvoton_pwm_readl(nvtpwm, MA35D1_REG_PWM_CTL1); + + if ((ctl1 & outmode_mask) && + nuvoton_pwm_channel_active(nvtpwm, ch ^ 1)) + return -EBUSY; + + /* + * IMMLDENn = 0, WINLDENn = 0 and CTRLDn = 0 select period loading + * mode for up-counting operation. + */ + ctl0_mask = MA35D1_PWM_CTL0_IMMLDEN(ch); + ctl0_mask |= MA35D1_PWM_CTL0_WINLDEN(ch); + ctl0_mask |= MA35D1_PWM_CTL0_CTRLD(ch); + + /* + * CNTTYPEn = 00: up counter type + * CNTMODEn = 0: auto-reload mode + * OUTMODEn = 0: independent mode + */ + ctl1_mask = MA35D1_PWM_CTL1_CNTTYPE_MASK(ch); + ctl1_mask |= MA35D1_PWM_CTL1_CNTMODE_MASK(ch); + ctl1_mask |= outmode_mask; + + /* + * ZPCTLn = 10: output high at zero point + * PRDPCTLn = 00: do nothing at period point + */ + wgctl0_mask = MA35D1_PWM_WGCTL_ACTION(ch); + wgctl0_mask |= MA35D1_PWM_WGCTL_ACTION(ch) << 16; + wgctl0_val = MA35D1_PWM_WGCTL_ACTION_VAL(ch, + MA35D1_PWM_WGCTL_ACTION_HIGH); + + /* + * CMPUCTLn = 01: output low at compare up point + * CMPDCTLn = 00: do nothing at compare down point + */ + wgctl1_mask = MA35D1_PWM_WGCTL_ACTION(ch); + wgctl1_mask |= MA35D1_PWM_WGCTL_ACTION(ch) << 16; + wgctl1_val = MA35D1_PWM_WGCTL_ACTION_VAL(ch, + MA35D1_PWM_WGCTL_ACTION_LOW); + + nuvoton_pwm_rmw(nvtpwm, MA35D1_REG_PWM_CTL0, ctl0_mask, 0); + nuvoton_pwm_rmw(nvtpwm, MA35D1_REG_PWM_CTL1, ctl1_mask, 0); + nuvoton_pwm_rmw(nvtpwm, MA35D1_REG_PWM_WGCTL0, + wgctl0_mask, wgctl0_val); + nuvoton_pwm_rmw(nvtpwm, MA35D1_REG_PWM_WGCTL1, + wgctl1_mask, wgctl1_val); + + return 0; +} + +static int nuvoton_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct nuvoton_pwm *nvtpwm = nuvoton_pwm_from_chip(chip); + unsigned int ch = pwm->hwpwm; + u64 duty_cycles, period_cycles; + u64 divisor; + u32 cmpdat, period, prescale; + int ret; + + if (!state->enabled) { + nuvoton_pwm_rmw(nvtpwm, MA35D1_REG_PWM_POEN, + MA35D1_PWM_POEN_EN(ch), 0); + nuvoton_pwm_rmw(nvtpwm, MA35D1_REG_PWM_CNTEN, + MA35D1_PWM_CNTEN_EN(ch), 0); + + return 0; + } + + prescale = nuvoton_pwm_get_prescale(nvtpwm, ch); + divisor = (u64)NSEC_PER_SEC * (prescale + 1); + + period_cycles = mul_u64_u64_div_u64(nvtpwm->clkrate, + state->period, divisor); + if (!period_cycles) + return -EINVAL; + + if (period_cycles > MA35D1_PWM_MAX_CYCLES) + period_cycles = MA35D1_PWM_MAX_CYCLES; + + duty_cycles = mul_u64_u64_div_u64(nvtpwm->clkrate, + state->duty_cycle, divisor); + if (duty_cycles > period_cycles) + duty_cycles = period_cycles; + + ret = nuvoton_pwm_config_channel(nvtpwm, ch); + if (ret) + return ret; + + if (state->polarity == PWM_POLARITY_NORMAL) + nuvoton_pwm_rmw(nvtpwm, MA35D1_REG_PWM_POLCTL, + MA35D1_PWM_POLCTL_INV(ch), 0); + else + nuvoton_pwm_rmw(nvtpwm, MA35D1_REG_PWM_POLCTL, + MA35D1_PWM_POLCTL_INV(ch), + MA35D1_PWM_POLCTL_INV(ch)); + + /* + * In up-counting mode the counter counts from 0 to PERIOD inclusive. + * With zero point high and compare-up point low actions: + * - CMPDAT = 0 produces 0% duty. + * - CMPDAT > PERIOD produces 100% duty. + * + * period_cycles is limited to 0xffff, so PERIOD is at most 0xfffe + * and a 100% duty cycle can be represented by CMPDAT = 0xffff. + */ + period = period_cycles - 1; + cmpdat = duty_cycles; + + nuvoton_pwm_writel(nvtpwm, MA35D1_REG_PWM_PERIOD(ch), period); + nuvoton_pwm_writel(nvtpwm, MA35D1_REG_PWM_CMPDAT(ch), cmpdat); + + nuvoton_pwm_rmw(nvtpwm, MA35D1_REG_PWM_POEN, + MA35D1_PWM_POEN_EN(ch), MA35D1_PWM_POEN_EN(ch)); + nuvoton_pwm_rmw(nvtpwm, MA35D1_REG_PWM_CNTEN, + MA35D1_PWM_CNTEN_EN(ch), MA35D1_PWM_CNTEN_EN(ch)); + + return 0; +} + +static int nuvoton_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct nuvoton_pwm *nvtpwm = nuvoton_pwm_from_chip(chip); + unsigned int ch = pwm->hwpwm; + u32 cmpdat, cnten, period, poen, polctl, prescale; + u64 duty_cycles, period_cycles; + u64 prescaled_cycles; + + cnten = nuvoton_pwm_readl(nvtpwm, MA35D1_REG_PWM_CNTEN); + poen = nuvoton_pwm_readl(nvtpwm, MA35D1_REG_PWM_POEN); + polctl = nuvoton_pwm_readl(nvtpwm, MA35D1_REG_PWM_POLCTL); + prescale = nuvoton_pwm_get_prescale(nvtpwm, ch); + period = nuvoton_pwm_readl(nvtpwm, MA35D1_REG_PWM_PERIOD(ch)) & + MA35D1_PWM_DATA_MASK; + cmpdat = nuvoton_pwm_readl(nvtpwm, MA35D1_REG_PWM_CMPDAT(ch)) & + MA35D1_PWM_DATA_MASK; + + period_cycles = period + 1; + if (cmpdat > period) + duty_cycles = period_cycles; + else + duty_cycles = cmpdat; + + state->enabled = (cnten & MA35D1_PWM_CNTEN_EN(ch)) && + (poen & MA35D1_PWM_POEN_EN(ch)); + state->polarity = (polctl & MA35D1_PWM_POLCTL_INV(ch)) ? + PWM_POLARITY_INVERSED : PWM_POLARITY_NORMAL; + + prescaled_cycles = period_cycles * (prescale + 1); + state->period = DIV64_U64_ROUND_UP(prescaled_cycles * NSEC_PER_SEC, + nvtpwm->clkrate); + + prescaled_cycles = duty_cycles * (prescale + 1); + state->duty_cycle = + DIV64_U64_ROUND_UP(prescaled_cycles * NSEC_PER_SEC, + nvtpwm->clkrate); + + return 0; +} + +static const struct pwm_ops nuvoton_pwm_ops = { + .apply = nuvoton_pwm_apply, + .get_state = nuvoton_pwm_get_state, +}; + +static int nuvoton_pwm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pwm_chip *chip; + struct nuvoton_pwm *nvtpwm; + struct clk *clk; + int ret; + + chip = devm_pwmchip_alloc(dev, MA35D1_PWM_NUM_CHANNELS, + sizeof(*nvtpwm)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + + nvtpwm = nuvoton_pwm_from_chip(chip); + + nvtpwm->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(nvtpwm->base)) + return PTR_ERR(nvtpwm->base); + + clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), + "Unable to get the clock\n"); + + ret = devm_clk_rate_exclusive_get(dev, clk); + if (ret) + return dev_err_probe(dev, ret, + "Unable to get exclusive clock rate\n"); + + nvtpwm->clkrate = clk_get_rate(clk); + if (!nvtpwm->clkrate) + return dev_err_probe(dev, -EINVAL, + "PWM clock rate is zero\n"); + + if (nvtpwm->clkrate > NSEC_PER_SEC) + return dev_err_probe(dev, -EINVAL, + "PWM clock out of range (%lu)\n", + nvtpwm->clkrate); + + chip->ops = &nuvoton_pwm_ops; + chip->atomic = true; + + ret = devm_pwmchip_add(dev, chip); + if (ret) + return dev_err_probe(dev, ret, "Unable to add PWM chip\n"); + + return 0; +} + +static const struct of_device_id nuvoton_pwm_of_match[] = { + { .compatible = "nuvoton,ma35d1-pwm" }, + { } +}; +MODULE_DEVICE_TABLE(of, nuvoton_pwm_of_match); + +static struct platform_driver nuvoton_pwm_driver = { + .probe = nuvoton_pwm_probe, + .driver = { + .name = "nuvoton-pwm", + .of_match_table = nuvoton_pwm_of_match, + }, +}; +module_platform_driver(nuvoton_pwm_driver); + +MODULE_AUTHOR("Chi-Wen Weng "); +MODULE_DESCRIPTION("Nuvoton MA35D1 PWM driver"); +MODULE_LICENSE("GPL"); -- 2.25.1