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Wed, 14 Oct 2026 11:04:37 +0000 From: Hal Feng To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Hal Feng , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v23 1/2] dt-bindings: pwm: opencores: Update compatibles, examples and maintainers Date: Wed, 14 Oct 2026 19:04:28 +0800 Message-ID: <20261014110429.52762-2-hal.feng@starfivetech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20261014110429.52762-1-hal.feng@starfivetech.com> References: <20261014110429.52762-1-hal.feng@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: NT0PR01CA0020.CHNPR01.prod.partner.outlook.cn (2406:e500:c510:c::16) To NT0PR01MB1102.CHNPR01.prod.partner.outlook.cn (2406:e500:c510:7::10) Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: NT0PR01MB1102:EE_|NT0PR01MB1069:EE_ X-MS-Office365-Filtering-Correlation-Id: 24f99af6-a1d3-4a8b-da6a-08df29e2efb3 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|366016|52116014|23010399003|38350700014|56012099006|261009223027099003|260925022911599003|260925021911599003|260925021311599003|10067099003|18002099003|22082099003|3023799007; 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Change the register size in examples to 0x10, since an OpenCores PTC IP has only 4 32-bit registers: CNTR, HRC, LRC and CTRL. I will maintain this pwm module in place of William. Tested-by: Maud Spierings Acked-by: Conor Dooley Fixes: 2529085831b0 ("dt-bindings: pwm: Add bindings for OpenCores PWM Controller") Signed-off-by: Hal Feng --- Documentation/devicetree/bindings/pwm/opencores,pwm.yaml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml index 52a59d245cdb..b15468f97b59 100644 --- a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: OpenCores PWM controller maintainers: - - William Qiu + - Hal Feng description: The OpenCores PTC ip core contains a PWM controller. When operating in PWM @@ -23,7 +23,6 @@ properties: - enum: - starfive,jh7100-pwm - starfive,jh7110-pwm - - starfive,jh8100-pwm - const: opencores,pwm-v1 reg: @@ -49,7 +48,7 @@ examples: - | pwm@12490000 { compatible = "starfive,jh7110-pwm", "opencores,pwm-v1"; - reg = <0x12490000 0x10000>; + reg = <0x12490000 0x10>; clocks = <&clkgen 181>; resets = <&rstgen 109>; #pwm-cells = <3>; -- 2.43.2