Re: [PATCH 07/11] dt-bindings: clock: renesas,r8a78000-cpg: Add PWM clocks

[Laurent Pinchart <laurent.pinchart@ideasonboard.com>]

On Thu, Oct 29, 2026 at 10:08:28AM +0100, Geert Uytterhoeven wrote:
> On Wed, 28 Oct 2026 at 17:39, Laurent Pinchart wrote:
> > On Wed, Oct 28, 2026 at 03:43:42PM +0100, Geert Uytterhoeven wrote:
> > > On Wed, 28 Oct 2026 at 14:29, Laurent Pinchart wrote:
> > > > On Mon, Oct 26, 2026 at 03:55:23PM +0100, Geert Uytterhoeven wrote:
> > > > > Add definitions for the clocks used by the PWM modules on R-Car X5H:
> > > > >  - R8A78000_CPG_SGASYNCD16_PERW_MAIN,
> > > > >  - R8A78000_CPG_S0ASYNCD8_PERW_MAIN.
> > > > > Include R8A78000_CPG_SGASYNCD8_PERW_MAIN for ordering consistency.
> > > > >
> > > > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > >
> > > > > --- a/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> > > > > +++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> > > > > @@ -28,5 +28,8 @@
> > > > >  #define R8A78000_CPG_SGD8_PERW_BUS           18
> > > > >  #define R8A78000_CPG_SGD32_PERW_BUS          19
> > > > >  #define R8A78000_CPG_S0D24_HSCN_OTHER                20
> > > > > +#define R8A78000_CPG_SGASYNCD8_PERW_MAIN     21
> > > > > +#define R8A78000_CPG_SGASYNCD16_PERW_MAIN    22
> > > >
> > > > Could you also add R8A78000_CPG_SGASYNCD4_PERW_MAIN and
> > > > R8A78000_CPG_SGASYNCD32_PERW_MAIN for ordering consistency ? The
> > > > dependency patch should then also include R8A78000_CPG_SGD4_PERW_BUS and
> > > > R8A78000_CPG_SGD16_PERW_BUS, as well as
> > > > R8A78000_CPG_S0D{1,2,4,8,12,16}_HSCN_OTHER.
> > >
> > > I could add them, but do you have any need to refer to them from DT?
> > > So far I only added clocks that are listed as clock supplies of on-SoC
> > > modules, e.g. R8A78000_CPG_SGASYNCD8_PERW_MAIN is supplied to the
> > > Timer Unit (TMU)).
> >
> > So we have two conflicting goals here. One of them is to only add clocks
> > that we have validated to exist (and ideally work as documented). The
> > other is to keep renesas,r8a78000-cpg.h readable. We won't be able to
> > satisfy them both fully.
> >
> > I think we previously discussed adding whole groups of dividers in one
> > go, as some sort of middle-ground approach. Those are clocks that are
> 
> That is what did in this and the previous patch: we need
>   - R8A78000_CPG_SGASYNCDn_PERW_MAIN for n=16, and added the one for
>     n=8, too.

That's missing n=4 and n=32. While SGASYNCD32 isn't referenced in the
datasheet, SGASYNCD4 is (in SCIF and HSCIF). Maybe that's just an
oversight ?

>   - R8A78000_CPG_SCPBUSDn_SCP_MAIN for n=16, and added the ones for
>     n=1,2,4,6,8,32, too.
>   - R8A78000_CPG_S0Dn_PERE_MAIN for n=24, and added the ones for
>     n=1,2,3,4,8, too.
>   - R8A78000_CPG_SGDn_PERW_BUS for n=32, and added the ones for n=8,
>     too.
> 
> I did not includes clocks with values for n that exist according to
> the documentation, but are not used as suppliers for modules.
> Of course the documentation may be incorrect or incomplete, and we may
> need to add them later. As IDs are ABI and the list is append-only,
> they must be added at the end, which could indeed lead to not all
> clocks of the same group being located together.  From an ABI point
> of view that is OK, but from a human-readability point of view it is
> indeed suboptimal.
> 
> Before, we tended to add all clocks from the clock tables listed the
> documentation upfront, ignoring clocks that are clearly internal-only.
> Some of them turned out not to exist later.
> Some new clocks had to be added when the documentation was updated.
> Nothing new here, except that the list of clocks on R-Car X5H is an
> order of magnitude longer.
> 
> Note that we don't use a linear array of clocks indexed by clock ID
> in the R-Car X5H CPG driver (yet), so large holes of unused clocks do
> not hurt (they do hurt in the SCMI driver ;-)
> 
> > not directly controllable. There's a risk of adding clocks that don't
> 
> FTR, the xDn clocks are not directly controllable; clocks like
> R8A78000_CPG_MSO_SCP_MAIN are.  We know the latter exist, as they
> are used.

Yes, I was talking about the clocks documented in the various
non-PLL "hierarchy" sections.

> > exist, or clocks that we won't need to reference from DT (because
> > they're only used as parents of the MDLC-controlled module clock). Do
> 
> The direct parent of an MDLC-controlled module clock should be in DT.

An additional difficulty is that we don't actually know what clocks the
MDLC gates :-/

> Higher-up parents should not be needed iff the SCMI firmware exposed
> and/or implements the proper clock hierarchy (which it does not at
> the moment).

A big *iff* :-)

Even in that case, we'll have (at least) two issues:

- Some modules may need to know the rate of the functional clock gated
  by the MDLC. As those clocks are controlled through power domains,
  they are only specified as the last cell of the power-domains
  property, and are not listed in the clocks property. How do you
  envision this to work ?

- When multiple clocks derive from the same PLL, it's common for the PLL
  rate to be specified through assigned-clock-rates. If we want to
  continue doing that, we need to to make the whole clock hierarchy
  available to DT.

> Still, they can be internal enum, starting after the last
> DT clock, like we did in other R-Car clock drivers.
> 
> > you think that's an issue, could it cause ABI problems in the future ?
> 
> An ABI problem appears only when you refer in DT to a clock that does
> not exist in hardware.  This should be caught by testing before the
> DT user is added.

So we could add e.g. SGASYNCD32 already, as long as we don't reference
it in DT without testing.

-- 
Regards,

Laurent Pinchart