From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C91DD35E95C; Mon, 23 Mar 2026 07:24:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774250692; cv=none; b=XIfjl81Yss002LlewJ7t8rF3YXliNFbpKV0AeHvwcff6ep704zAlHi3RP1kBbA9sDsvsKBPJLfJE5cDBO0BqnxTZhExbDaNw48yjzKWKVt6KiKLJOVm8Rbu4Zm1ULuwGJ/XZS3ke23SciMVefuc36Cb4f4Kr0QQ9GB+rZTbtato= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774250692; c=relaxed/simple; bh=NjNq7kW0nQDF61cbcfgcT5KIPc4deicQ9CCz8WFnpfM=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=TPkLKOgDVpLGzw40YZmuWOetUo3or+1hCAlsj0JqbD4EIO7KEjJLh9Hr4p99nhEzQUOMVlgOetkwZZQocegJKxV7qFGxU8pZmzQY/vsZvSUb4Iqjy34a4EtuPrXjVFPZWInl4S7JLW7jtxEI7Mfi6Kogo0zEVKsZeAo1GxHJaJA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=u6SMIQGE; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="u6SMIQGE" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5B921C4CEF7; Mon, 23 Mar 2026 07:24:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774250691; bh=NjNq7kW0nQDF61cbcfgcT5KIPc4deicQ9CCz8WFnpfM=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=u6SMIQGE8u4sB1Orsg3zFkXOlDCHJG9DrX4SLapYuwq6s5QeVfPylaOrPhvblykrH P+4taE+NUu9mjqbGOyQItU2pIdm4auQoqIGFLhPtGGoXNhOmZEx+kyTJsJUy1g0G9l OmYTX7Y3AQkKxA7Nsq6aQQtBBVuhvCYZUzV+TSuDxSKS0j7fzOEl0V/WQdfOAkUZHC Ry65APiTpzisuhW4gDgn3YTFXerQzUyhub187jHIlDXQoy4+V6Cw+94XDIm7aaxyWC FmQzmyqD0/mqqmmrNHHg5+WI99ak9lE64ROAl3LhV7N4v06m5RH39c/3NQe/1CvW0H KRXDYvKD05eKQ== Message-ID: <26c43bb4-d6d3-41ff-926a-597ee1392e83@kernel.org> Date: Mon, 23 Mar 2026 08:24:47 +0100 Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/5] Tegra264 PWM support To: Mikko Perttunen , Thierry Reding , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , Jonathan Hunter Cc: linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Yi-Wei Wang References: <20260323-t264-pwm-v1-0-4c4ff743050f@nvidia.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 23/03/2026 03:36, Mikko Perttunen wrote: > Hello, > > this adds support for the PWM controller on Tegra264. The controller > is similar to previous generations, but the register fields are > widened, the depth is made configurable, and the enable bit moves > to a different spot. > > This series adds only basic support with fixed depth -- configurable > depth will come later. > > The series uses the nvidia,tegra264-pwm compatible string. Bindings > for this are added in Thierry's series > > https://lore.kernel.org/linux-tegra/20260320234056.2579010-1-thierry.reding@kernel.org/ NAK, that's not how you send driver code. Best regards, Krzysztof