From: "Yu-Chun Lin [林祐君]" <eleanor.lin@realtek.com>
To: Conor Dooley <conor@kernel.org>, Linus Walleij <linusw@kernel.org>
Cc: "Uwe Kleine-König" <ukleinek@kernel.org>,
"linux-pwm@vger.kernel.org" <linux-pwm@vger.kernel.org>,
"robh@kernel.org" <robh@kernel.org>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"brgl@kernel.org" <brgl@kernel.org>,
"James Tai [戴志峰]" <james.tai@realtek.com>,
"CY_Huang[黃鉦晏]" <cy.huang@realtek.com>,
"Stanley Chang[昌育德]" <stanley_chang@realtek.com>,
"TY_Chang[張子逸]" <tychang@realtek.com>
Subject: RE: [PATCH 5/8] dt-bindings: pinctrl: realtek: add RTD1625 pinctrl binding
Date: Thu, 26 Feb 2026 10:47:30 +0000 [thread overview]
Message-ID: <7450228dba6a4497b4cdf23747f5830b@realtek.com> (raw)
In-Reply-To: <20260225-reconvene-troubling-947eb972cef8@spud>
> On Wed, Jan 28, 2026 at 01:33:00PM +0100, Linus Walleij wrote:
> > Hi Yu-Chun,
> >
> > thanks for your patch!
> >
> > [Uwe, can you check this a bit down!]
> >
> > On Wed, Jan 28, 2026 at 4:39 AM Yu-Chun Lin <eleanor.lin@realtek.com> wrote:
> >
> > From: Tzuyi Chang <tychang@realtek.com>
> >
> > Add device tree bindings for RTD1625.
> >
> > > Signed-off-by: Tzuyi Chang <tychang@realtek.com>
> > > Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> > > Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
> >
> > Overall this looks good!
>
> Where can I find the binding patch? What this is in-reply-to does not
> exist:
> https://lore.kernel.org/all/CAD++jL=445wx467ZKE3-qm_BaVzKYXE-7zmReTFZA0KUAaSNyw@mail.gmail.com/
> Nor can I find anything else from Eleanor that would appear to be what this is:
> https://lore.kernel.org/all/?q=f%3Aeleanor.lin%40realtek.com
>
Hi Conor,
I apologize for the confusion. I realized that when I sent out the v1 patch, I
missed the mailing list, which is why it's not showing up in the archives.
Since I had already received some feedback on v1, I missed the timing to resend the v1.
However, you were included in the CC list of the initial v1 patch email.
You might be able to find the full patch in your inbox.
> >
> > > + power-source:
> > > + description: |
> > > + Valid arguments are described as below:
> > > + 0: power supply of 1.8V
> > > + 1: power supply of 3.3V
> > > + enum: [0, 1]
> >
> > OK...
> >
> > > + slew-rate:
> > > + description: |
> > > + Valid arguments are described as below:
> > > + 0: ~1ns falling time
> > > + 1: ~10ns falling time
> > > + 2: ~20ns falling time
> > > + 3: ~30ns falling time
> > > + enum: [0, 1, 2, 3]
> >
> > Slew rate is usually something like volts/second in SI units, I would
> > expect that this differs depending on which power-source is selected?
> > I.e. are these values for 1.8V or 3.3V?
> >
> > > + realtek,drive-strength-p:
> > > + description: |
> > > + Some of pins can be driven using the P-MOS and N-MOS transistor to
> > > + achieve finer adjustments.
> >
> > Finer compared to what? Compared to the overall setting for slew-rate
> > or drive-strength, or both?
> >
> > > The block-diagram representation is as
> > > + follows:
> > > + VDD
> > > + |
> > > + ||--+
> > > + +-----o|| P-MOS-FET
> > > + | ||--+
> > > + IN --+ +----- out
> > > + | ||--+
> > > + +------|| N-MOS-FET
> > > + ||--+
> > > + |
> > > + GND
> >
> > Nice picture!
> >
> > > + The driving strength of the P-MOS/N-MOS transistors impacts the
> > > + waveform's rise/fall times. Greater driving strength results in
> > > + shorter rise/fall times. Each P-MOS and N-MOS transistor offers
> > > + 8 configurable levels (0 to 7), with higher values indicating
> > > + greater driving strength, contributing to achieving the desired
> > > + speed.
> > > +
> > > + The realtek,drive-strength-p is used to control the driving strength
> > > + of the P-MOS output.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + minimum: 0
> > > + maximum: 7
> > > +
> > > + realtek,drive-strength-n:
> > > + description: |
> > > + Similar to the realtek,drive-strength-p, the realtek,drive-strength-n
> > > + is used to control the driving strength of the N-MOS output.
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + minimum: 0
> > > + maximum: 7
> >
> > These two are really interesting. But what do these settings represent?
> >
> > I would *guess* it represents the number of transistors used, simply,
> > so 0 means just one P/N transistor is driving and 7 means 8
> > transistors are driving.
> >
> > Can you provide details here?
> >
> > In this case, maybe we want a generalized property such as
> > drive-stages-p = <n>; drive-stages-n = <n>;
> >
> > in the generic bindings, if this will appear from more vendors?
> >
> > > + realtek,duty-cycle:
> > > + description: |
> > > + An integer describing the level to adjust output duty cycle,
> > > + controlling the proportion of positive and negative waveforms in
> > > + nanoseconds.
> > > + Valid arguments are described as below:
> > > + 0: 0ns
> > > + 2: + 0.25ns
> > > + 3: + 0.5ns
> > > + 4: -0.25ns
> > > + 5: -0.5ns
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + enum: [0, 2, 3, 4, 5]
> >
> > This is a bit dubious.
> >
> > Isn't this one of those cases where you should be using the PWM
> > bindings, directly in this node? Just slam in #pwm-cells = <...> etc,
> > I think this is what you really want.
> >
> > Please consult/reference:
> > Documentation/devicetree/bindings/pwm/pwm.yaml
> > consumers would not use pinctrl phandles but something like pwms =
> > <&pwm ....>;
> >
> > It's maybe a bit trixy to use two generic bindings in the node but it
> > should be just fine.
> >
> > I don't feel confident mergeing this without Uwe Kleine-König's review.
>
> This does sound like a pwm to me too, but I can't see the rest of the series to comment.
>
Please kindly refer to my response to Linus [1].
[1] https://lore.kernel.org/all/d5be357c14b84155adfa8a9f00a64d83@realtek.com/
>
> > > + realtek,input-voltage:
> > > + description: |
> > > + Select the input receiver voltage domain for the pin (1.8V or 3.3V).
> > > + This defines the reference for VIH/VIL and must match the external
> > > + signal level.
> > > +
> > > + This does not control the output drive voltage, which is handled by
> > > + the standard generic 'power-source' property.
> > > +
> > > + Valid arguments are described as below:
> > > + 0: 1.8V input logic level
> > > + 1: 3.3V input logic level
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + enum: [0, 1]
> >
> > This looks very generic. Can you please just add input-voltage to
> > pincfg-node.yaml with a custom format and reference that?
>
> Why a custom format, rather than input-voltage-microvolt or w/e?
>
I will add input-voltage-microvolt to pincfg-node.yaml and use the microvolt format
as suggested. Thanks
Yu-Chun
> Cheers,
> Conor.
>
> >
> > > + realtek,high-vil:
> > > + type: boolean
> > > + description: |
> > > + Select the input receiver with a higher LOW recognition threshold
> > > + (VIL) to improve detection for sources with weak pull-down or slow
> > > + falling edges.
> >
> > Isn't this supposed to be input-schmitt-microvolt?
> >
> > Or is this something else than a schmitt trigger?
> >
> > In either case, try to figure out the typical recognition threshold in
> > microvolt and use that, please.
> >
> > Yours,
> > Linus Walleij
next prev parent reply other threads:[~2026-02-26 10:47 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20260128033936.27642-1-eleanor.lin@realtek.com>
[not found] ` <20260128033936.27642-6-eleanor.lin@realtek.com>
2026-01-28 12:33 ` [PATCH 5/8] dt-bindings: pinctrl: realtek: add RTD1625 pinctrl binding Linus Walleij
2026-01-29 10:38 ` Uwe Kleine-König
2026-01-30 2:22 ` Yu-Chun Lin [林祐君]
2026-02-25 9:30 ` Yu-Chun Lin [林祐君]
2026-02-27 0:08 ` Linus Walleij
2026-02-25 18:03 ` Conor Dooley
2026-02-26 10:47 ` Yu-Chun Lin [林祐君] [this message]
2026-02-26 11:15 ` Conor Dooley
[not found] ` <20260128033936.27642-7-eleanor.lin@realtek.com>
2026-01-28 12:37 ` [PATCH 6/8] pinctrl: realtek: add support for slew rate, input voltage and high VIL Linus Walleij
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