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Fri, 23 May 2025 02:09:20 -0700 (PDT) Message-ID: <92107be5d4085f934c725d31177aae00b971984d.camel@gmail.com> Subject: Re: [PATCH v2 3/3] pwm: axi-pwmgen: fix missing separate external clock From: Nuno =?ISO-8859-1?Q?S=E1?= To: David Lechner , Michael Hennerich , Nuno =?ISO-8859-1?Q?S=E1?= , Trevor Gamblin , Uwe =?ISO-8859-1?Q?Kleine-K=F6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 23 May 2025 10:09:22 +0100 In-Reply-To: <20250522-pwm-axi-pwmgen-add-external-clock-v2-3-086ea9e6ecf0@baylibre.com> References: <20250522-pwm-axi-pwmgen-add-external-clock-v2-0-086ea9e6ecf0@baylibre.com> <20250522-pwm-axi-pwmgen-add-external-clock-v2-3-086ea9e6ecf0@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.1 Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Thu, 2025-05-22 at 09:49 -0500, David Lechner wrote: > Add proper support for external clock to the AXI PWM generator driver. >=20 > In most cases, the HDL for this IP block is compiled with the default > ASYNC_CLK_EN=3D1. With this option, there is a separate external clock > that drives the PWM output separate from the peripheral clock. So the > driver should be enabling the "axi" clock to power the peripheral and > the "ext" clock to drive the PWM output. >=20 > When ASYNC_CLK_EN=3D0, the "axi" clock is also used to drive the PWM > output and there is no "ext" clock. >=20 > Previously, if there was a separate external clock, users had to specify > only the external clock and (incorrectly) omit the AXI clock in order > to get the correct operating frequency for the PWM output. >=20 > The devicetree bindings are updated to fix this shortcoming and this > patch changes the driver to match the new bindings. To preserve > compatibility with any existing dtbs that specify only one clock, we > don't require the clock name on the first clock. >=20 > Fixes: 41814fe5c782 ("pwm: Add driver for AXI PWM generator") > Signed-off-by: David Lechner > --- Acked-by: Nuno S=C3=A1 > =C2=A0drivers/pwm/pwm-axi-pwmgen.c | 23 ++++++++++++++++++++--- > =C2=A01 file changed, 20 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c > index > 4337c8f5acf055fc87dc134f2a70b99b0cb5ede6..60dcd354237316bced2d951b7f0b116= c8291 > bb0d 100644 > --- a/drivers/pwm/pwm-axi-pwmgen.c > +++ b/drivers/pwm/pwm-axi-pwmgen.c > @@ -257,7 +257,7 @@ static int axi_pwmgen_probe(struct platform_device *p= dev) > =C2=A0 struct regmap *regmap; > =C2=A0 struct pwm_chip *chip; > =C2=A0 struct axi_pwmgen_ddata *ddata; > - struct clk *clk; > + struct clk *axi_clk, *clk; > =C2=A0 void __iomem *io_base; > =C2=A0 int ret; > =C2=A0 > @@ -280,9 +280,26 @@ static int axi_pwmgen_probe(struct platform_device *= pdev) > =C2=A0 ddata =3D pwmchip_get_drvdata(chip); > =C2=A0 ddata->regmap =3D regmap; > =C2=A0 > - clk =3D devm_clk_get_enabled(dev, NULL); > + /* > + * Using NULL here instead of "axi" for backwards compatibility. > There > + * are some dtbs that don't give clock-names and have the "ext" clock > + * as the one and only clock (due to mistake in the original > bindings). > + */ > + axi_clk =3D devm_clk_get_enabled(dev, NULL); > + if (IS_ERR(axi_clk)) > + return dev_err_probe(dev, PTR_ERR(axi_clk), "failed to get > axi clock\n"); > + > + clk =3D devm_clk_get_optional_enabled(dev, "ext"); > =C2=A0 if (IS_ERR(clk)) > - return dev_err_probe(dev, PTR_ERR(clk), "failed to get > clock\n"); > + return dev_err_probe(dev, PTR_ERR(clk), "failed to get ext > clock\n"); > + > + /* > + * If there is no "ext" clock, it means the HDL was compiled with > + * ASYNC_CLK_EN=3D0. In this case, the AXI clock is also used for the > + * PWM output clock. > + */ > + if (!clk) > + clk =3D axi_clk; > =C2=A0 > =C2=A0 ret =3D devm_clk_rate_exclusive_get(dev, clk); > =C2=A0 if (ret)