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[2003:e4:1f05:3a00:f22f:74ff:fe1f:3a53]) by smtp.gmail.com with ESMTPSA id p24-20020a170906615800b00923f05b2931sm6335951ejl.118.2023.04.17.02.17.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Apr 2023 02:17:59 -0700 (PDT) Date: Mon, 17 Apr 2023 11:17:57 +0200 From: Thierry Reding To: Neil Armstrong Cc: Heiner Kallweit , Jerome Brunet , Martin Blumenstingl , Neil Armstrong , Kevin Hilman , Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= , "linux-arm-kernel@lists.infradead.org" , "open list:ARM/Amlogic Meson..." , linux-pwm@vger.kernel.org Subject: Re: [PATCH v4 4/4] pwm: meson: make full use of common clock framework Message-ID: References: <9faca2e6-b7a1-4748-7eb0-48f8064e323e@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="viCwK5jD5+sqkLig" Content-Disposition: inline In-Reply-To: User-Agent: Mutt/2.2.10 (2023-03-25) Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org --viCwK5jD5+sqkLig Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Apr 17, 2023 at 09:23:35AM +0200, Neil Armstrong wrote: > On 13/04/2023 07:54, Heiner Kallweit wrote: [...] > > diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c [...] > > @@ -271,16 +255,16 @@ static int meson_pwm_apply(struct pwm_chip *chip,= struct pwm_device *pwm, > > /* > > * This IP block revision doesn't have an "always high" > > * setting which we can use for "inverted disabled". > > - * Instead we achieve this using the same settings > > - * that we use a pre_div of 0 (to get the shortest > > - * possible duration for one "count") and > > + * Instead we achieve this by setting an arbitrary, > > + * very high frequency, resulting in the shortest > > + * possible duration for one "count" and > > * "period =3D=3D duty_cycle". This results in a signal > > * which is LOW for one "count", while being HIGH for > > * the rest of the (so the signal is HIGH for slightly > > * less than 100% of the period, but this is the best > > * we can achieve). > > */ > > - channel->pre_div =3D 0; > > + channel->rate =3D 1000000000; > > channel->hi =3D ~0; > > channel->lo =3D 0; >=20 > This looks like a really bad idea... please don't do that and instead int= roduce > some pinctrl states where we set the PWM pin as GPIO mode high/low state = like we > did for SPI: > https://lore.kernel.org/r/20221004-up-aml-fix-spi-v4-2-0342d8e10c49@bayli= bre.com Yeah, absolutely. If the pin controller can do that, that's the right way to implement the desired behavior. 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