* [PATCH 0/7] Add RZ/G3E support
@ 2025-08-14 18:41 Biju
2025-08-14 18:41 ` [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document " Biju
` (4 more replies)
0 siblings, 5 replies; 13+ messages in thread
From: Biju @ 2025-08-14 18:41 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-pwm, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add RZ/G3E GPT support. It has multiple clocks and resets compared to
RZ/G2L. Also prescale field width and factor for calculating prescale
are different.
This patch has dependency on [1]
[1] https://lore.kernel.org/all/20250814115022.73732-1-biju.das.jz@bp.renesas.com/
Biju Das (7):
dt-bindings: pwm: renesas,rzg2l-gpt: Document RZ/G3E support
pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip
pwm: rzg2l-gpt: Add prescale_pow_of_two_mult_factor variable to struct
rzg2l_gpt_info
pwm: rzg2l-gpt: Add calculate_prescale() callback to struct
rzg2l_gpt_info
pwm: rzg2l-gpt: Add RZ/G3E support
arm64: dts: renesas: r9a09g047: Add GPT nodes
arm64: dts: renesas: r9a09g047e57-smarc: Enable GPT on carrier board
.../bindings/pwm/renesas,rzg2l-gpt.yaml | 525 ++++++++++++------
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 184 ++++++
.../boot/dts/renesas/r9a09g047e57-smarc.dts | 13 +
drivers/pwm/pwm-rzg2l-gpt.c | 93 +++-
4 files changed, 633 insertions(+), 182 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document RZ/G3E support
2025-08-14 18:41 [PATCH 0/7] Add RZ/G3E support Biju
@ 2025-08-14 18:41 ` Biju
2025-08-19 16:18 ` Tommaso Merciai
2025-08-20 20:29 ` Rob Herring
2025-08-14 18:41 ` [PATCH 2/7] pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip Biju
` (3 subsequent siblings)
4 siblings, 2 replies; 13+ messages in thread
From: Biju @ 2025-08-14 18:41 UTC (permalink / raw)
To: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-pwm, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Document support for the GPT found on the Renesas RZ/G3E (R9A09G047)
SoC.
The GPT IP on these parts is similar to that on RZ/G2L but supports
only 8 interrupts per channel and has multiple clocks and resets.
Introduce a new compatible string `renesas,r9a09g047-gpt` for RZ/G3E.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../bindings/pwm/renesas,rzg2l-gpt.yaml | 525 ++++++++++++------
1 file changed, 356 insertions(+), 169 deletions(-)
diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
index 13b807765a30..6250dbb200e7 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
+++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
@@ -58,11 +58,14 @@ description: |
properties:
compatible:
- items:
- - enum:
- - renesas,r9a07g044-gpt # RZ/G2{L,LC}
- - renesas,r9a07g054-gpt # RZ/V2L
- - const: renesas,rzg2l-gpt
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r9a07g044-gpt # RZ/G2{L,LC}
+ - renesas,r9a07g054-gpt # RZ/V2L
+ - const: renesas,rzg2l-gpt
+
+ - const: renesas,r9a09g047-gpt # RZ/G3E
reg:
maxItems: 1
@@ -71,179 +74,327 @@ properties:
const: 3
interrupts:
- items:
- - description: GPT32E0.GTCCRA input capture/compare match
- - description: GPT32E0.GTCCRB input capture/compare
- - description: GPT32E0.GTCCRC compare match
- - description: GPT32E0.GTCCRD compare match
- - description: GPT32E0.GTCCRE compare match
- - description: GPT32E0.GTCCRF compare match
- - description: GPT32E0.GTADTRA compare match
- - description: GPT32E0.GTADTRB compare match
- - description: GPT32E0.GTCNT overflow/GTPR compare match
- - description: GPT32E0.GTCNT underflow
- - description: GPT32E1.GTCCRA input capture/compare match
- - description: GPT32E1.GTCCRB input capture/compare
- - description: GPT32E1.GTCCRC compare match
- - description: GPT32E1.GTCCRD compare match
- - description: GPT32E1.GTCCRE compare match
- - description: GPT32E1.GTCCRF compare match
- - description: GPT32E1.GTADTRA compare match
- - description: GPT32E1.GTADTRB compare match
- - description: GPT32E1.GTCNT overflow/GTPR compare match
- - description: GPT32E1.GTCNT underflow
- - description: GPT32E2.GTCCRA input capture/compare match
- - description: GPT32E2.GTCCRB input capture/compare
- - description: GPT32E2.GTCCRC compare match
- - description: GPT32E2.GTCCRD compare match
- - description: GPT32E2.GTCCRE compare match
- - description: GPT32E2.GTCCRF compare match
- - description: GPT32E2.GTADTRA compare match
- - description: GPT32E2.GTADTRB compare match
- - description: GPT32E2.GTCNT overflow/GTPR compare match
- - description: GPT32E2.GTCNT underflow
- - description: GPT32E3.GTCCRA input capture/compare match
- - description: GPT32E3.GTCCRB input capture/compare
- - description: GPT32E3.GTCCRC compare match
- - description: GPT32E3.GTCCRD compare match
- - description: GPT32E3.GTCCRE compare match
- - description: GPT32E3.GTCCRF compare match
- - description: GPT32E3.GTADTRA compare match
- - description: GPT32E3.GTADTRB compare match
- - description: GPT32E3.GTCNT overflow/GTPR compare match
- - description: GPT32E3.GTCNT underflow
- - description: GPT32E4.GTCCRA input capture/compare match
- - description: GPT32E4.GTCCRB input capture/compare
- - description: GPT32E4.GTCCRC compare match
- - description: GPT32E4.GTCCRD compare match
- - description: GPT32E4.GTCCRE compare match
- - description: GPT32E4.GTCCRF compare match
- - description: GPT32E4.GTADTRA compare match
- - description: GPT32E4.GTADTRB compare match
- - description: GPT32E4.GTCNT overflow/GTPR compare match
- - description: GPT32E4.GTCNT underflow
- - description: GPT32E5.GTCCRA input capture/compare match
- - description: GPT32E5.GTCCRB input capture/compare
- - description: GPT32E5.GTCCRC compare match
- - description: GPT32E5.GTCCRD compare match
- - description: GPT32E5.GTCCRE compare match
- - description: GPT32E5.GTCCRF compare match
- - description: GPT32E5.GTADTRA compare match
- - description: GPT32E5.GTADTRB compare match
- - description: GPT32E5.GTCNT overflow/GTPR compare match
- - description: GPT32E5.GTCNT underflow
- - description: GPT32E6.GTCCRA input capture/compare match
- - description: GPT32E6.GTCCRB input capture/compare
- - description: GPT32E6.GTCCRC compare match
- - description: GPT32E6.GTCCRD compare match
- - description: GPT32E6.GTCCRE compare match
- - description: GPT32E6.GTCCRF compare match
- - description: GPT32E6.GTADTRA compare match
- - description: GPT32E6.GTADTRB compare match
- - description: GPT32E6.GTCNT overflow/GTPR compare match
- - description: GPT32E6.GTCNT underflow
- - description: GPT32E7.GTCCRA input capture/compare match
- - description: GPT32E7.GTCCRB input capture/compare
- - description: GPT32E7.GTCCRC compare match
- - description: GPT32E7.GTCCRD compare match
- - description: GPT32E7.GTCCRE compare match
- - description: GPT32E7.GTCCRF compare match
- - description: GPT32E7.GTADTRA compare match
- - description: GPT32E7.GTADTRB compare match
- - description: GPT32E7.GTCNT overflow/GTPR compare match
- - description: GPT32E7.GTCNT underflow
+ oneOf:
+ - items:
+ - description: GPT32E0.GTCCRA input capture/compare match
+ - description: GPT32E0.GTCCRB input capture/compare
+ - description: GPT32E0.GTCCRC compare match
+ - description: GPT32E0.GTCCRD compare match
+ - description: GPT32E0.GTCCRE compare match
+ - description: GPT32E0.GTCCRF compare match
+ - description: GPT32E0.GTADTRA compare match
+ - description: GPT32E0.GTADTRB compare match
+ - description: GPT32E0.GTCNT overflow/GTPR compare match
+ - description: GPT32E0.GTCNT underflow
+ - description: GPT32E1.GTCCRA input capture/compare match
+ - description: GPT32E1.GTCCRB input capture/compare
+ - description: GPT32E1.GTCCRC compare match
+ - description: GPT32E1.GTCCRD compare match
+ - description: GPT32E1.GTCCRE compare match
+ - description: GPT32E1.GTCCRF compare match
+ - description: GPT32E1.GTADTRA compare match
+ - description: GPT32E1.GTADTRB compare match
+ - description: GPT32E1.GTCNT overflow/GTPR compare match
+ - description: GPT32E1.GTCNT underflow
+ - description: GPT32E2.GTCCRA input capture/compare match
+ - description: GPT32E2.GTCCRB input capture/compare
+ - description: GPT32E2.GTCCRC compare match
+ - description: GPT32E2.GTCCRD compare match
+ - description: GPT32E2.GTCCRE compare match
+ - description: GPT32E2.GTCCRF compare match
+ - description: GPT32E2.GTADTRA compare match
+ - description: GPT32E2.GTADTRB compare match
+ - description: GPT32E2.GTCNT overflow/GTPR compare match
+ - description: GPT32E2.GTCNT underflow
+ - description: GPT32E3.GTCCRA input capture/compare match
+ - description: GPT32E3.GTCCRB input capture/compare
+ - description: GPT32E3.GTCCRC compare match
+ - description: GPT32E3.GTCCRD compare match
+ - description: GPT32E3.GTCCRE compare match
+ - description: GPT32E3.GTCCRF compare match
+ - description: GPT32E3.GTADTRA compare match
+ - description: GPT32E3.GTADTRB compare match
+ - description: GPT32E3.GTCNT overflow/GTPR compare match
+ - description: GPT32E3.GTCNT underflow
+ - description: GPT32E4.GTCCRA input capture/compare match
+ - description: GPT32E4.GTCCRB input capture/compare
+ - description: GPT32E4.GTCCRC compare match
+ - description: GPT32E4.GTCCRD compare match
+ - description: GPT32E4.GTCCRE compare match
+ - description: GPT32E4.GTCCRF compare match
+ - description: GPT32E4.GTADTRA compare match
+ - description: GPT32E4.GTADTRB compare match
+ - description: GPT32E4.GTCNT overflow/GTPR compare match
+ - description: GPT32E4.GTCNT underflow
+ - description: GPT32E5.GTCCRA input capture/compare match
+ - description: GPT32E5.GTCCRB input capture/compare
+ - description: GPT32E5.GTCCRC compare match
+ - description: GPT32E5.GTCCRD compare match
+ - description: GPT32E5.GTCCRE compare match
+ - description: GPT32E5.GTCCRF compare match
+ - description: GPT32E5.GTADTRA compare match
+ - description: GPT32E5.GTADTRB compare match
+ - description: GPT32E5.GTCNT overflow/GTPR compare match
+ - description: GPT32E5.GTCNT underflow
+ - description: GPT32E6.GTCCRA input capture/compare match
+ - description: GPT32E6.GTCCRB input capture/compare
+ - description: GPT32E6.GTCCRC compare match
+ - description: GPT32E6.GTCCRD compare match
+ - description: GPT32E6.GTCCRE compare match
+ - description: GPT32E6.GTCCRF compare match
+ - description: GPT32E6.GTADTRA compare match
+ - description: GPT32E6.GTADTRB compare match
+ - description: GPT32E6.GTCNT overflow/GTPR compare match
+ - description: GPT32E6.GTCNT underflow
+ - description: GPT32E7.GTCCRA input capture/compare match
+ - description: GPT32E7.GTCCRB input capture/compare
+ - description: GPT32E7.GTCCRC compare match
+ - description: GPT32E7.GTCCRD compare match
+ - description: GPT32E7.GTCCRE compare match
+ - description: GPT32E7.GTCCRF compare match
+ - description: GPT32E7.GTADTRA compare match
+ - description: GPT32E7.GTADTRB compare match
+ - description: GPT32E7.GTCNT overflow/GTPR compare match
+ - description: GPT32E7.GTCNT underflow
+ - items:
+ - description: Input capture/compare match of the GTCCRA for channel 0 and 8
+ - description: Input capture/compare match of the GTCCRB for channel 0 and 8
+ - description: Compare match with the GTCCRC for channel 0 and 8
+ - description: Compare match with the GTCCRD for channel 0 and 8
+ - description: Compare match with the GTCCRE for channel 0 and 8
+ - description: Compare match with the GTCCRF for channel 0 and 8
+ - description: A and B both high interrupt for channel 0 and 8
+ - description: A and B both low interrupt for channel 0 and 8
+ - description: Input capture/compare match of the GTCCRA for channel 1 and 9
+ - description: Input capture/compare match of the GTCCRB for channel 1 and 9
+ - description: Compare match with the GTCCRC for channel 1 and 9
+ - description: Compare match with the GTCCRD for channel 1 and 9
+ - description: Compare match with the GTCCRE for channel 1 and 9
+ - description: Compare match with the GTCCRF for channel 1 and 9
+ - description: A and B both high interrupt for channel 1 and 9
+ - description: A and B both low interrupt for channel 1 and 9
+ - description: Input capture/compare match of the GTCCRA for channel 2 and 10
+ - description: Input capture/compare match of the GTCCRB for channel 2 and 10
+ - description: Compare match with the GTCCRC for channel 2 and 10
+ - description: Compare match with the GTCCRD for channel 2 and 10
+ - description: Compare match with the GTCCRE for channel 2 and 10
+ - description: Compare match with the GTCCRF for channel 2 and 10
+ - description: A and B both high interrupt for channel 2 and 10
+ - description: A and B both low interrupt for channel 2 and 10
+ - description: Input capture/compare match of the GTCCRA for channel 3 and 11
+ - description: Input capture/compare match of the GTCCRB for channel 3 and 11
+ - description: Compare match with the GTCCRC for channel 3 and 11
+ - description: Compare match with the GTCCRD for channel 3 and 11
+ - description: Compare match with the GTCCRE for channel 3 and 11
+ - description: Compare match with the GTCCRF for channel 3 and 11
+ - description: A and B both high interrupt for channel 3 and 11
+ - description: A and B both low interrupt for channel 3 and 11
+ - description: Input capture/compare match of the GTCCRA for channel 4 and 12
+ - description: Input capture/compare match of the GTCCRB for channel 4 and 12
+ - description: Compare match with the GTCCRC for channel 4 and 12
+ - description: Compare match with the GTCCRD for channel 4 and 12
+ - description: Compare match with the GTCCRE for channel 4 and 12
+ - description: Compare match with the GTCCRF for channel 4 and 12
+ - description: A and B both high interrupt for channel 4 and 12
+ - description: A and B both low interrupt for channel 4 and 12
+ - description: Input capture/compare match of the GTCCRA for channel 5 and 13
+ - description: Input capture/compare match of the GTCCRB for channel 5 and 13
+ - description: Compare match with the GTCCRC for channel 5 and 13
+ - description: Compare match with the GTCCRD for channel 5 and 13
+ - description: Compare match with the GTCCRE for channel 5 and 13
+ - description: Compare match with the GTCCRF for channel 5 and 13
+ - description: A and B both high interrupt for channel 5 and 13
+ - description: A and B both low interrupt for channel 5 and 13
+ - description: Input capture/compare match of the GTCCRA for channel 6 and 14
+ - description: Input capture/compare match of the GTCCRB for channel 6 and 14
+ - description: Compare match with the GTCCRC for channel 6 and 14
+ - description: Compare match with the GTCCRD for channel 6 and 14
+ - description: Compare match with the GTCCRE for channel 6 and 14
+ - description: Compare match with the GTCCRF for channel 6 and 14
+ - description: A and B both high interrupt for channel 6 and 14
+ - description: A and B both low interrupt for channel 6 and 14
+ - description: Input capture/compare match of the GTCCRA for channel 7 and 15
+ - description: Input capture/compare match of the GTCCRB for channel 7 and 15
+ - description: Compare match with the GTCCRC for channel 7 and 15
+ - description: Compare match with the GTCCRD for channel 7 and 15
+ - description: Compare match with the GTCCRE for channel 7 and 15
+ - description: Compare match with the GTCCRF for channel 7 and 15
+ - description: A and B both high interrupt for channel 7 and 15
+ - description: A and B both low interrupt for channel 7 and 15
interrupt-names:
- items:
- - const: ccmpa0
- - const: ccmpb0
- - const: cmpc0
- - const: cmpd0
- - const: cmpe0
- - const: cmpf0
- - const: adtrga0
- - const: adtrgb0
- - const: ovf0
- - const: unf0
- - const: ccmpa1
- - const: ccmpb1
- - const: cmpc1
- - const: cmpd1
- - const: cmpe1
- - const: cmpf1
- - const: adtrga1
- - const: adtrgb1
- - const: ovf1
- - const: unf1
- - const: ccmpa2
- - const: ccmpb2
- - const: cmpc2
- - const: cmpd2
- - const: cmpe2
- - const: cmpf2
- - const: adtrga2
- - const: adtrgb2
- - const: ovf2
- - const: unf2
- - const: ccmpa3
- - const: ccmpb3
- - const: cmpc3
- - const: cmpd3
- - const: cmpe3
- - const: cmpf3
- - const: adtrga3
- - const: adtrgb3
- - const: ovf3
- - const: unf3
- - const: ccmpa4
- - const: ccmpb4
- - const: cmpc4
- - const: cmpd4
- - const: cmpe4
- - const: cmpf4
- - const: adtrga4
- - const: adtrgb4
- - const: ovf4
- - const: unf4
- - const: ccmpa5
- - const: ccmpb5
- - const: cmpc5
- - const: cmpd5
- - const: cmpe5
- - const: cmpf5
- - const: adtrga5
- - const: adtrgb5
- - const: ovf5
- - const: unf5
- - const: ccmpa6
- - const: ccmpb6
- - const: cmpc6
- - const: cmpd6
- - const: cmpe6
- - const: cmpf6
- - const: adtrga6
- - const: adtrgb6
- - const: ovf6
- - const: unf6
- - const: ccmpa7
- - const: ccmpb7
- - const: cmpc7
- - const: cmpd7
- - const: cmpe7
- - const: cmpf7
- - const: adtrga7
- - const: adtrgb7
- - const: ovf7
- - const: unf7
+ oneOf:
+ - items:
+ - const: ccmpa0
+ - const: ccmpb0
+ - const: cmpc0
+ - const: cmpd0
+ - const: cmpe0
+ - const: cmpf0
+ - const: adtrga0
+ - const: adtrgb0
+ - const: ovf0
+ - const: unf0
+ - const: ccmpa1
+ - const: ccmpb1
+ - const: cmpc1
+ - const: cmpd1
+ - const: cmpe1
+ - const: cmpf1
+ - const: adtrga1
+ - const: adtrgb1
+ - const: ovf1
+ - const: unf1
+ - const: ccmpa2
+ - const: ccmpb2
+ - const: cmpc2
+ - const: cmpd2
+ - const: cmpe2
+ - const: cmpf2
+ - const: adtrga2
+ - const: adtrgb2
+ - const: ovf2
+ - const: unf2
+ - const: ccmpa3
+ - const: ccmpb3
+ - const: cmpc3
+ - const: cmpd3
+ - const: cmpe3
+ - const: cmpf3
+ - const: adtrga3
+ - const: adtrgb3
+ - const: ovf3
+ - const: unf3
+ - const: ccmpa4
+ - const: ccmpb4
+ - const: cmpc4
+ - const: cmpd4
+ - const: cmpe4
+ - const: cmpf4
+ - const: adtrga4
+ - const: adtrgb4
+ - const: ovf4
+ - const: unf4
+ - const: ccmpa5
+ - const: ccmpb5
+ - const: cmpc5
+ - const: cmpd5
+ - const: cmpe5
+ - const: cmpf5
+ - const: adtrga5
+ - const: adtrgb5
+ - const: ovf5
+ - const: unf5
+ - const: ccmpa6
+ - const: ccmpb6
+ - const: cmpc6
+ - const: cmpd6
+ - const: cmpe6
+ - const: cmpf6
+ - const: adtrga6
+ - const: adtrgb6
+ - const: ovf6
+ - const: unf6
+ - const: ccmpa7
+ - const: ccmpb7
+ - const: cmpc7
+ - const: cmpd7
+ - const: cmpe7
+ - const: cmpf7
+ - const: adtrga7
+ - const: adtrgb7
+ - const: ovf7
+ - const: unf7
+ - items:
+ - const: gtcia0
+ - const: gtcib0
+ - const: gtcic0
+ - const: gtcid0
+ - const: gtcie0
+ - const: gtcif0
+ - const: gtcih0
+ - const: gtcil0
+ - const: gtcia1
+ - const: gtcib1
+ - const: gtcic1
+ - const: gtcid1
+ - const: gtcie1
+ - const: gtcif1
+ - const: gtcih1
+ - const: gtcil1
+ - const: gtcia2
+ - const: gtcib2
+ - const: gtcic2
+ - const: gtcid2
+ - const: gtcie2
+ - const: gtcif2
+ - const: gtcih2
+ - const: gtcil2
+ - const: gtcia3
+ - const: gtcib3
+ - const: gtcic3
+ - const: gtcid3
+ - const: gtcie3
+ - const: gtcif3
+ - const: gtcih3
+ - const: gtcil3
+ - const: gtcia4
+ - const: gtcib4
+ - const: gtcic4
+ - const: gtcid4
+ - const: gtcie4
+ - const: gtcif4
+ - const: gtcih4
+ - const: gtcil4
+ - const: gtcia5
+ - const: gtcib5
+ - const: gtcic5
+ - const: gtcid5
+ - const: gtcie5
+ - const: gtcif5
+ - const: gtcih5
+ - const: gtcil5
+ - const: gtcia6
+ - const: gtcib6
+ - const: gtcic6
+ - const: gtcid6
+ - const: gtcie6
+ - const: gtcif6
+ - const: gtcih6
+ - const: gtcil6
+ - const: gtcia7
+ - const: gtcib7
+ - const: gtcic7
+ - const: gtcid7
+ - const: gtcie7
+ - const: gtcif7
+ - const: gtcih7
+ - const: gtcil7
clocks:
- maxItems: 1
+ items:
+ - description: Core clock (PCLKD)
+ - description: Bus clock (PCLKA)
+ minItems: 1
+
+ clock-names:
+ items:
+ - const: core
+ - const: bus
power-domains:
maxItems: 1
resets:
- maxItems: 1
+ items:
+ - description: Reset for bus clock (PCLKA/PCLKD)
+ - description: Reset for core clock (PCLKD)
+ minItems: 1
+
+ reset-names:
+ items:
+ - const: rst_p
+ - const: rst_s
required:
- compatible
@@ -257,6 +408,42 @@ required:
allOf:
- $ref: pwm.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g047-gpt
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ resets:
+ minItems: 2
+ interrupts:
+ maxItems: 64
+ interrupt-names:
+ maxItems: 64
+
+ required:
+ - clock-names
+ - reset-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,rzg2l-gpt
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ resets:
+ maxItems: 1
+ interrupts:
+ minItems: 80
+ interrupt-names:
+ minItems: 80
+
additionalProperties: false
examples:
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/7] pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip
2025-08-14 18:41 [PATCH 0/7] Add RZ/G3E support Biju
2025-08-14 18:41 ` [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document " Biju
@ 2025-08-14 18:41 ` Biju
2025-08-19 16:20 ` Tommaso Merciai
2025-08-14 18:41 ` [PATCH 3/7] pwm: rzg2l-gpt: Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info Biju
` (2 subsequent siblings)
4 siblings, 1 reply; 13+ messages in thread
From: Biju @ 2025-08-14 18:41 UTC (permalink / raw)
To: Uwe Kleine-König, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-pwm, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
RZ/G3E GPT IP is similar to the one found on RZ/G2L GPT, but there are
some differences. The field width of prescalar on RZ/G3E is 4 whereas on
RZ/G2L it is 3. Add rzg2l_gpt_info variable to handle this differences.
The FIELD_PREP and FIELD_GET macro is giving compilation issue as the
parameters are not build time constants. So added Non-constant mask
variant of FIELD_GET() and FIELD_PREP().
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/pwm/pwm-rzg2l-gpt.c | 33 ++++++++++++++++++++++++++++-----
1 file changed, 28 insertions(+), 5 deletions(-)
diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index f0a8531457ca..bf989defa527 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -33,6 +33,19 @@
#include <linux/time.h>
#include <linux/units.h>
+/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
+#define field_get(_mask, _reg) \
+({\
+ typeof(_mask) (mask) = (_mask); \
+ (((_reg) & (mask)) >> (ffs(mask) - 1)); \
+})
+
+#define field_prep(_mask, _val) \
+({\
+ typeof(_mask) (mask) = (_mask); \
+ (((_val) << (ffs(mask) - 1)) & (mask)); \
+})
+
#define RZG2L_GET_CH(hwpwm) ((hwpwm) / 2)
#define RZG2L_GET_CH_OFFS(ch) (0x100 * (ch))
@@ -46,7 +59,6 @@
#define RZG2L_GTCR_CST BIT(0)
#define RZG2L_GTCR_MD GENMASK(18, 16)
-#define RZG2L_GTCR_TPCS GENMASK(26, 24)
#define RZG2L_GTCR_MD_SAW_WAVE_PWM_MODE FIELD_PREP(RZG2L_GTCR_MD, 0)
@@ -77,9 +89,14 @@
#define RZG2L_MAX_SCALE_FACTOR 1024
#define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR)
+struct rzg2l_gpt_info {
+ u32 gtcr_tpcs_mask;
+};
+
struct rzg2l_gpt_chip {
void __iomem *mmio;
struct mutex lock; /* lock to protect shared channel resources */
+ const struct rzg2l_gpt_info *info;
unsigned long rate_khz;
u32 period_ticks[RZG2L_MAX_HW_CHANNELS];
u32 channel_request_count[RZG2L_MAX_HW_CHANNELS];
@@ -317,7 +334,7 @@ static int rzg2l_gpt_read_waveform(struct pwm_chip *chip,
if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm)) {
gtcr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(ch));
- wfhw->prescale = FIELD_GET(RZG2L_GTCR_TPCS, gtcr);
+ wfhw->prescale = field_get(rzg2l_gpt->info->gtcr_tpcs_mask, gtcr);
wfhw->gtpr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch));
wfhw->gtccr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch));
if (wfhw->gtccr > wfhw->gtpr)
@@ -354,8 +371,8 @@ static int rzg2l_gpt_write_waveform(struct pwm_chip *chip,
rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTUDDTYC(ch), RZG2L_GTUDDTYC_UP_COUNTING);
/* Select count clock */
- rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_TPCS,
- FIELD_PREP(RZG2L_GTCR_TPCS, wfhw->prescale));
+ rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), rzg2l_gpt->info->gtcr_tpcs_mask,
+ field_prep(rzg2l_gpt->info->gtcr_tpcs_mask, wfhw->prescale));
/* Set period */
rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), wfhw->gtpr);
@@ -414,6 +431,8 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
if (IS_ERR(rzg2l_gpt->mmio))
return PTR_ERR(rzg2l_gpt->mmio);
+ rzg2l_gpt->info = of_device_get_match_data(dev);
+
rstc = devm_reset_control_get_exclusive_deasserted(dev, NULL);
if (IS_ERR(rstc))
return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\n");
@@ -456,8 +475,12 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
return 0;
}
+static const struct rzg2l_gpt_info rzg2l_data = {
+ .gtcr_tpcs_mask = GENMASK(26, 24),
+};
+
static const struct of_device_id rzg2l_gpt_of_table[] = {
- { .compatible = "renesas,rzg2l-gpt", },
+ { .compatible = "renesas,rzg2l-gpt", .data = &rzg2l_data },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, rzg2l_gpt_of_table);
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/7] pwm: rzg2l-gpt: Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info
2025-08-14 18:41 [PATCH 0/7] Add RZ/G3E support Biju
2025-08-14 18:41 ` [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document " Biju
2025-08-14 18:41 ` [PATCH 2/7] pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip Biju
@ 2025-08-14 18:41 ` Biju
2025-08-19 16:21 ` Tommaso Merciai
2025-08-14 18:41 ` [PATCH 4/7] pwm: rzg2l-gpt: Add calculate_prescale() callback " Biju
2025-08-14 18:41 ` [PATCH 5/7] pwm: rzg2l-gpt: Add RZ/G3E support Biju
4 siblings, 1 reply; 13+ messages in thread
From: Biju @ 2025-08-14 18:41 UTC (permalink / raw)
To: Uwe Kleine-König, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-pwm, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
RZ/G3E GPT IP has prescale factor power of 2 where as that of RZ/G2L is 4.
Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info for
handling this difference.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/pwm/pwm-rzg2l-gpt.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index bf989defa527..74bb0cca4ab4 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -91,6 +91,7 @@
struct rzg2l_gpt_info {
u32 gtcr_tpcs_mask;
+ u8 prescale_pow_of_two_mult_factor;
};
struct rzg2l_gpt_chip {
@@ -226,6 +227,7 @@ static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *rzg2l_gpt,
static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,
u32 val, u8 prescale)
{
+ const struct rzg2l_gpt_info *info = rzg2l_gpt->info;
u64 tmp;
/*
@@ -235,15 +237,18 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,
* < 2^32 * 2^10 * 2^20
* = 2^62
*/
- tmp = (u64)val << (2 * prescale);
+ tmp = (u64)val << (info->prescale_pow_of_two_mult_factor * prescale);
tmp *= USEC_PER_SEC;
return DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz);
}
-static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale)
+static u32 rzg2l_gpt_calculate_pv_or_dc(const struct rzg2l_gpt_info *info,
+ u64 period_or_duty_cycle, u8 prescale)
{
- return min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * prescale)),
+ return min_t(u64,
+ DIV_ROUND_DOWN_ULL(period_or_duty_cycle,
+ 1 << (info->prescale_pow_of_two_mult_factor * prescale)),
U32_MAX);
}
@@ -254,6 +259,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,
{
struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
+ const struct rzg2l_gpt_info *info = rzg2l_gpt->info;
struct rzg2l_gpt_waveform *wfhw = _wfhw;
u8 ch = RZG2L_GET_CH(pwm->hwpwm);
u64 period_ticks, duty_ticks;
@@ -287,12 +293,12 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,
}
wfhw->prescale = rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks);
- pv = rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale);
+ pv = rzg2l_gpt_calculate_pv_or_dc(info, period_ticks, wfhw->prescale);
wfhw->gtpr = pv;
duty_ticks = mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_khz, USEC_PER_SEC);
if (duty_ticks > period_ticks)
duty_ticks = period_ticks;
- dc = rzg2l_gpt_calculate_pv_or_dc(duty_ticks, wfhw->prescale);
+ dc = rzg2l_gpt_calculate_pv_or_dc(info, duty_ticks, wfhw->prescale);
wfhw->gtccr = dc;
/*
@@ -477,6 +483,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
static const struct rzg2l_gpt_info rzg2l_data = {
.gtcr_tpcs_mask = GENMASK(26, 24),
+ .prescale_pow_of_two_mult_factor = 2,
};
static const struct of_device_id rzg2l_gpt_of_table[] = {
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/7] pwm: rzg2l-gpt: Add calculate_prescale() callback to struct rzg2l_gpt_info
2025-08-14 18:41 [PATCH 0/7] Add RZ/G3E support Biju
` (2 preceding siblings ...)
2025-08-14 18:41 ` [PATCH 3/7] pwm: rzg2l-gpt: Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info Biju
@ 2025-08-14 18:41 ` Biju
2025-08-19 16:22 ` Tommaso Merciai
2025-08-14 18:41 ` [PATCH 5/7] pwm: rzg2l-gpt: Add RZ/G3E support Biju
4 siblings, 1 reply; 13+ messages in thread
From: Biju @ 2025-08-14 18:41 UTC (permalink / raw)
To: Uwe Kleine-König, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-pwm, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
RZ/G2L GPT the prescale factors are continuous power of 4 whereas on RZ/G3E
it is power of 2 but discontinuous. Add calculate_prescale() callback to
struct rzg2l_gpt_info for handling this difference.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/pwm/pwm-rzg2l-gpt.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index 74bb0cca4ab4..b247a6c181d5 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -90,6 +90,7 @@
#define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR)
struct rzg2l_gpt_info {
+ u8 (*calculate_prescale)(u64 period);
u32 gtcr_tpcs_mask;
u8 prescale_pow_of_two_mult_factor;
};
@@ -138,8 +139,7 @@ static void rzg2l_gpt_modify(struct rzg2l_gpt_chip *rzg2l_gpt, u32 reg, u32 clr,
(rzg2l_gpt_read(rzg2l_gpt, reg) & ~clr) | set);
}
-static u8 rzg2l_gpt_calculate_prescale(struct rzg2l_gpt_chip *rzg2l_gpt,
- u64 period_ticks)
+static u8 rzg2l_gpt_calculate_prescale(u64 period_ticks)
{
u32 prescaled_period_ticks;
u8 prescale;
@@ -292,7 +292,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,
period_ticks = rzg2l_gpt->period_ticks[ch];
}
- wfhw->prescale = rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks);
+ wfhw->prescale = info->calculate_prescale(period_ticks);
pv = rzg2l_gpt_calculate_pv_or_dc(info, period_ticks, wfhw->prescale);
wfhw->gtpr = pv;
duty_ticks = mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_khz, USEC_PER_SEC);
@@ -482,6 +482,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
}
static const struct rzg2l_gpt_info rzg2l_data = {
+ .calculate_prescale = rzg2l_gpt_calculate_prescale,
.gtcr_tpcs_mask = GENMASK(26, 24),
.prescale_pow_of_two_mult_factor = 2,
};
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 5/7] pwm: rzg2l-gpt: Add RZ/G3E support
2025-08-14 18:41 [PATCH 0/7] Add RZ/G3E support Biju
` (3 preceding siblings ...)
2025-08-14 18:41 ` [PATCH 4/7] pwm: rzg2l-gpt: Add calculate_prescale() callback " Biju
@ 2025-08-14 18:41 ` Biju
2025-08-19 16:23 ` Tommaso Merciai
4 siblings, 1 reply; 13+ messages in thread
From: Biju @ 2025-08-14 18:41 UTC (permalink / raw)
To: Uwe Kleine-König, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-pwm, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add RZ/G3E GPT support. It has multiple clocks and resets compared to
RZ/G2L. Also prescale field width and factor for calculating prescale
are different.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/pwm/pwm-rzg2l-gpt.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
index b247a6c181d5..7047359cac63 100644
--- a/drivers/pwm/pwm-rzg2l-gpt.c
+++ b/drivers/pwm/pwm-rzg2l-gpt.c
@@ -153,6 +153,27 @@ static u8 rzg2l_gpt_calculate_prescale(u64 period_ticks)
return prescale;
}
+static u8 rzg3e_gpt_calculate_prescale(u64 period_ticks)
+{
+ u32 prescaled_period_ticks;
+ u8 prescale;
+
+ prescaled_period_ticks = period_ticks >> 32;
+ if (prescaled_period_ticks >= 64 && prescaled_period_ticks < 256) {
+ prescale = 6;
+ } else if (prescaled_period_ticks >= 256 && prescaled_period_ticks < 1024) {
+ prescale = 8;
+ } else if (prescaled_period_ticks >= 1024) {
+ prescale = 10;
+ } else {
+ prescale = fls(prescaled_period_ticks);
+ if (prescale > 1)
+ prescale -= 1;
+ }
+
+ return prescale;
+}
+
static int rzg2l_gpt_request(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
@@ -443,6 +464,14 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
if (IS_ERR(rstc))
return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\n");
+ rstc = devm_reset_control_get_optional_exclusive_deasserted(dev, "rst_s");
+ if (IS_ERR(rstc))
+ return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert rst_s reset\n");
+
+ clk = devm_clk_get_optional_enabled(dev, "bus");
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk), "Cannot get bus clock\n");
+
clk = devm_clk_get_enabled(dev, NULL);
if (IS_ERR(clk))
return dev_err_probe(dev, PTR_ERR(clk), "Cannot get clock\n");
@@ -481,6 +510,12 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
return 0;
}
+static const struct rzg2l_gpt_info rzg3e_data = {
+ .calculate_prescale = rzg3e_gpt_calculate_prescale,
+ .gtcr_tpcs_mask = GENMASK(26, 23),
+ .prescale_pow_of_two_mult_factor = 1,
+};
+
static const struct rzg2l_gpt_info rzg2l_data = {
.calculate_prescale = rzg2l_gpt_calculate_prescale,
.gtcr_tpcs_mask = GENMASK(26, 24),
@@ -488,6 +523,7 @@ static const struct rzg2l_gpt_info rzg2l_data = {
};
static const struct of_device_id rzg2l_gpt_of_table[] = {
+ { .compatible = "renesas,r9a09g047-gpt", .data = &rzg3e_data },
{ .compatible = "renesas,rzg2l-gpt", .data = &rzg2l_data },
{ /* Sentinel */ }
};
--
2.43.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document RZ/G3E support
2025-08-14 18:41 ` [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document " Biju
@ 2025-08-19 16:18 ` Tommaso Merciai
2025-08-20 20:29 ` Rob Herring
1 sibling, 0 replies; 13+ messages in thread
From: Tommaso Merciai @ 2025-08-19 16:18 UTC (permalink / raw)
To: Biju
Cc: Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm, Biju Das,
linux-pwm, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad
Hi Biju,
Thank you for the patch.
On Thu, Aug 14, 2025 at 07:41:05PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document support for the GPT found on the Renesas RZ/G3E (R9A09G047)
> SoC.
>
> The GPT IP on these parts is similar to that on RZ/G2L but supports
> only 8 interrupts per channel and has multiple clocks and resets.
> Introduce a new compatible string `renesas,r9a09g047-gpt` for RZ/G3E.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> ---
> .../bindings/pwm/renesas,rzg2l-gpt.yaml | 525 ++++++++++++------
> 1 file changed, 356 insertions(+), 169 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> index 13b807765a30..6250dbb200e7 100644
> --- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> +++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
> @@ -58,11 +58,14 @@ description: |
>
> properties:
> compatible:
> - items:
> - - enum:
> - - renesas,r9a07g044-gpt # RZ/G2{L,LC}
> - - renesas,r9a07g054-gpt # RZ/V2L
> - - const: renesas,rzg2l-gpt
> + oneOf:
> + - items:
> + - enum:
> + - renesas,r9a07g044-gpt # RZ/G2{L,LC}
> + - renesas,r9a07g054-gpt # RZ/V2L
> + - const: renesas,rzg2l-gpt
> +
> + - const: renesas,r9a09g047-gpt # RZ/G3E
>
> reg:
> maxItems: 1
> @@ -71,179 +74,327 @@ properties:
> const: 3
>
> interrupts:
> - items:
> - - description: GPT32E0.GTCCRA input capture/compare match
> - - description: GPT32E0.GTCCRB input capture/compare
> - - description: GPT32E0.GTCCRC compare match
> - - description: GPT32E0.GTCCRD compare match
> - - description: GPT32E0.GTCCRE compare match
> - - description: GPT32E0.GTCCRF compare match
> - - description: GPT32E0.GTADTRA compare match
> - - description: GPT32E0.GTADTRB compare match
> - - description: GPT32E0.GTCNT overflow/GTPR compare match
> - - description: GPT32E0.GTCNT underflow
> - - description: GPT32E1.GTCCRA input capture/compare match
> - - description: GPT32E1.GTCCRB input capture/compare
> - - description: GPT32E1.GTCCRC compare match
> - - description: GPT32E1.GTCCRD compare match
> - - description: GPT32E1.GTCCRE compare match
> - - description: GPT32E1.GTCCRF compare match
> - - description: GPT32E1.GTADTRA compare match
> - - description: GPT32E1.GTADTRB compare match
> - - description: GPT32E1.GTCNT overflow/GTPR compare match
> - - description: GPT32E1.GTCNT underflow
> - - description: GPT32E2.GTCCRA input capture/compare match
> - - description: GPT32E2.GTCCRB input capture/compare
> - - description: GPT32E2.GTCCRC compare match
> - - description: GPT32E2.GTCCRD compare match
> - - description: GPT32E2.GTCCRE compare match
> - - description: GPT32E2.GTCCRF compare match
> - - description: GPT32E2.GTADTRA compare match
> - - description: GPT32E2.GTADTRB compare match
> - - description: GPT32E2.GTCNT overflow/GTPR compare match
> - - description: GPT32E2.GTCNT underflow
> - - description: GPT32E3.GTCCRA input capture/compare match
> - - description: GPT32E3.GTCCRB input capture/compare
> - - description: GPT32E3.GTCCRC compare match
> - - description: GPT32E3.GTCCRD compare match
> - - description: GPT32E3.GTCCRE compare match
> - - description: GPT32E3.GTCCRF compare match
> - - description: GPT32E3.GTADTRA compare match
> - - description: GPT32E3.GTADTRB compare match
> - - description: GPT32E3.GTCNT overflow/GTPR compare match
> - - description: GPT32E3.GTCNT underflow
> - - description: GPT32E4.GTCCRA input capture/compare match
> - - description: GPT32E4.GTCCRB input capture/compare
> - - description: GPT32E4.GTCCRC compare match
> - - description: GPT32E4.GTCCRD compare match
> - - description: GPT32E4.GTCCRE compare match
> - - description: GPT32E4.GTCCRF compare match
> - - description: GPT32E4.GTADTRA compare match
> - - description: GPT32E4.GTADTRB compare match
> - - description: GPT32E4.GTCNT overflow/GTPR compare match
> - - description: GPT32E4.GTCNT underflow
> - - description: GPT32E5.GTCCRA input capture/compare match
> - - description: GPT32E5.GTCCRB input capture/compare
> - - description: GPT32E5.GTCCRC compare match
> - - description: GPT32E5.GTCCRD compare match
> - - description: GPT32E5.GTCCRE compare match
> - - description: GPT32E5.GTCCRF compare match
> - - description: GPT32E5.GTADTRA compare match
> - - description: GPT32E5.GTADTRB compare match
> - - description: GPT32E5.GTCNT overflow/GTPR compare match
> - - description: GPT32E5.GTCNT underflow
> - - description: GPT32E6.GTCCRA input capture/compare match
> - - description: GPT32E6.GTCCRB input capture/compare
> - - description: GPT32E6.GTCCRC compare match
> - - description: GPT32E6.GTCCRD compare match
> - - description: GPT32E6.GTCCRE compare match
> - - description: GPT32E6.GTCCRF compare match
> - - description: GPT32E6.GTADTRA compare match
> - - description: GPT32E6.GTADTRB compare match
> - - description: GPT32E6.GTCNT overflow/GTPR compare match
> - - description: GPT32E6.GTCNT underflow
> - - description: GPT32E7.GTCCRA input capture/compare match
> - - description: GPT32E7.GTCCRB input capture/compare
> - - description: GPT32E7.GTCCRC compare match
> - - description: GPT32E7.GTCCRD compare match
> - - description: GPT32E7.GTCCRE compare match
> - - description: GPT32E7.GTCCRF compare match
> - - description: GPT32E7.GTADTRA compare match
> - - description: GPT32E7.GTADTRB compare match
> - - description: GPT32E7.GTCNT overflow/GTPR compare match
> - - description: GPT32E7.GTCNT underflow
> + oneOf:
> + - items:
> + - description: GPT32E0.GTCCRA input capture/compare match
> + - description: GPT32E0.GTCCRB input capture/compare
> + - description: GPT32E0.GTCCRC compare match
> + - description: GPT32E0.GTCCRD compare match
> + - description: GPT32E0.GTCCRE compare match
> + - description: GPT32E0.GTCCRF compare match
> + - description: GPT32E0.GTADTRA compare match
> + - description: GPT32E0.GTADTRB compare match
> + - description: GPT32E0.GTCNT overflow/GTPR compare match
> + - description: GPT32E0.GTCNT underflow
> + - description: GPT32E1.GTCCRA input capture/compare match
> + - description: GPT32E1.GTCCRB input capture/compare
> + - description: GPT32E1.GTCCRC compare match
> + - description: GPT32E1.GTCCRD compare match
> + - description: GPT32E1.GTCCRE compare match
> + - description: GPT32E1.GTCCRF compare match
> + - description: GPT32E1.GTADTRA compare match
> + - description: GPT32E1.GTADTRB compare match
> + - description: GPT32E1.GTCNT overflow/GTPR compare match
> + - description: GPT32E1.GTCNT underflow
> + - description: GPT32E2.GTCCRA input capture/compare match
> + - description: GPT32E2.GTCCRB input capture/compare
> + - description: GPT32E2.GTCCRC compare match
> + - description: GPT32E2.GTCCRD compare match
> + - description: GPT32E2.GTCCRE compare match
> + - description: GPT32E2.GTCCRF compare match
> + - description: GPT32E2.GTADTRA compare match
> + - description: GPT32E2.GTADTRB compare match
> + - description: GPT32E2.GTCNT overflow/GTPR compare match
> + - description: GPT32E2.GTCNT underflow
> + - description: GPT32E3.GTCCRA input capture/compare match
> + - description: GPT32E3.GTCCRB input capture/compare
> + - description: GPT32E3.GTCCRC compare match
> + - description: GPT32E3.GTCCRD compare match
> + - description: GPT32E3.GTCCRE compare match
> + - description: GPT32E3.GTCCRF compare match
> + - description: GPT32E3.GTADTRA compare match
> + - description: GPT32E3.GTADTRB compare match
> + - description: GPT32E3.GTCNT overflow/GTPR compare match
> + - description: GPT32E3.GTCNT underflow
> + - description: GPT32E4.GTCCRA input capture/compare match
> + - description: GPT32E4.GTCCRB input capture/compare
> + - description: GPT32E4.GTCCRC compare match
> + - description: GPT32E4.GTCCRD compare match
> + - description: GPT32E4.GTCCRE compare match
> + - description: GPT32E4.GTCCRF compare match
> + - description: GPT32E4.GTADTRA compare match
> + - description: GPT32E4.GTADTRB compare match
> + - description: GPT32E4.GTCNT overflow/GTPR compare match
> + - description: GPT32E4.GTCNT underflow
> + - description: GPT32E5.GTCCRA input capture/compare match
> + - description: GPT32E5.GTCCRB input capture/compare
> + - description: GPT32E5.GTCCRC compare match
> + - description: GPT32E5.GTCCRD compare match
> + - description: GPT32E5.GTCCRE compare match
> + - description: GPT32E5.GTCCRF compare match
> + - description: GPT32E5.GTADTRA compare match
> + - description: GPT32E5.GTADTRB compare match
> + - description: GPT32E5.GTCNT overflow/GTPR compare match
> + - description: GPT32E5.GTCNT underflow
> + - description: GPT32E6.GTCCRA input capture/compare match
> + - description: GPT32E6.GTCCRB input capture/compare
> + - description: GPT32E6.GTCCRC compare match
> + - description: GPT32E6.GTCCRD compare match
> + - description: GPT32E6.GTCCRE compare match
> + - description: GPT32E6.GTCCRF compare match
> + - description: GPT32E6.GTADTRA compare match
> + - description: GPT32E6.GTADTRB compare match
> + - description: GPT32E6.GTCNT overflow/GTPR compare match
> + - description: GPT32E6.GTCNT underflow
> + - description: GPT32E7.GTCCRA input capture/compare match
> + - description: GPT32E7.GTCCRB input capture/compare
> + - description: GPT32E7.GTCCRC compare match
> + - description: GPT32E7.GTCCRD compare match
> + - description: GPT32E7.GTCCRE compare match
> + - description: GPT32E7.GTCCRF compare match
> + - description: GPT32E7.GTADTRA compare match
> + - description: GPT32E7.GTADTRB compare match
> + - description: GPT32E7.GTCNT overflow/GTPR compare match
> + - description: GPT32E7.GTCNT underflow
> + - items:
> + - description: Input capture/compare match of the GTCCRA for channel 0 and 8
> + - description: Input capture/compare match of the GTCCRB for channel 0 and 8
> + - description: Compare match with the GTCCRC for channel 0 and 8
> + - description: Compare match with the GTCCRD for channel 0 and 8
> + - description: Compare match with the GTCCRE for channel 0 and 8
> + - description: Compare match with the GTCCRF for channel 0 and 8
> + - description: A and B both high interrupt for channel 0 and 8
> + - description: A and B both low interrupt for channel 0 and 8
> + - description: Input capture/compare match of the GTCCRA for channel 1 and 9
> + - description: Input capture/compare match of the GTCCRB for channel 1 and 9
> + - description: Compare match with the GTCCRC for channel 1 and 9
> + - description: Compare match with the GTCCRD for channel 1 and 9
> + - description: Compare match with the GTCCRE for channel 1 and 9
> + - description: Compare match with the GTCCRF for channel 1 and 9
> + - description: A and B both high interrupt for channel 1 and 9
> + - description: A and B both low interrupt for channel 1 and 9
> + - description: Input capture/compare match of the GTCCRA for channel 2 and 10
> + - description: Input capture/compare match of the GTCCRB for channel 2 and 10
> + - description: Compare match with the GTCCRC for channel 2 and 10
> + - description: Compare match with the GTCCRD for channel 2 and 10
> + - description: Compare match with the GTCCRE for channel 2 and 10
> + - description: Compare match with the GTCCRF for channel 2 and 10
> + - description: A and B both high interrupt for channel 2 and 10
> + - description: A and B both low interrupt for channel 2 and 10
> + - description: Input capture/compare match of the GTCCRA for channel 3 and 11
> + - description: Input capture/compare match of the GTCCRB for channel 3 and 11
> + - description: Compare match with the GTCCRC for channel 3 and 11
> + - description: Compare match with the GTCCRD for channel 3 and 11
> + - description: Compare match with the GTCCRE for channel 3 and 11
> + - description: Compare match with the GTCCRF for channel 3 and 11
> + - description: A and B both high interrupt for channel 3 and 11
> + - description: A and B both low interrupt for channel 3 and 11
> + - description: Input capture/compare match of the GTCCRA for channel 4 and 12
> + - description: Input capture/compare match of the GTCCRB for channel 4 and 12
> + - description: Compare match with the GTCCRC for channel 4 and 12
> + - description: Compare match with the GTCCRD for channel 4 and 12
> + - description: Compare match with the GTCCRE for channel 4 and 12
> + - description: Compare match with the GTCCRF for channel 4 and 12
> + - description: A and B both high interrupt for channel 4 and 12
> + - description: A and B both low interrupt for channel 4 and 12
> + - description: Input capture/compare match of the GTCCRA for channel 5 and 13
> + - description: Input capture/compare match of the GTCCRB for channel 5 and 13
> + - description: Compare match with the GTCCRC for channel 5 and 13
> + - description: Compare match with the GTCCRD for channel 5 and 13
> + - description: Compare match with the GTCCRE for channel 5 and 13
> + - description: Compare match with the GTCCRF for channel 5 and 13
> + - description: A and B both high interrupt for channel 5 and 13
> + - description: A and B both low interrupt for channel 5 and 13
> + - description: Input capture/compare match of the GTCCRA for channel 6 and 14
> + - description: Input capture/compare match of the GTCCRB for channel 6 and 14
> + - description: Compare match with the GTCCRC for channel 6 and 14
> + - description: Compare match with the GTCCRD for channel 6 and 14
> + - description: Compare match with the GTCCRE for channel 6 and 14
> + - description: Compare match with the GTCCRF for channel 6 and 14
> + - description: A and B both high interrupt for channel 6 and 14
> + - description: A and B both low interrupt for channel 6 and 14
> + - description: Input capture/compare match of the GTCCRA for channel 7 and 15
> + - description: Input capture/compare match of the GTCCRB for channel 7 and 15
> + - description: Compare match with the GTCCRC for channel 7 and 15
> + - description: Compare match with the GTCCRD for channel 7 and 15
> + - description: Compare match with the GTCCRE for channel 7 and 15
> + - description: Compare match with the GTCCRF for channel 7 and 15
> + - description: A and B both high interrupt for channel 7 and 15
> + - description: A and B both low interrupt for channel 7 and 15
>
> interrupt-names:
> - items:
> - - const: ccmpa0
> - - const: ccmpb0
> - - const: cmpc0
> - - const: cmpd0
> - - const: cmpe0
> - - const: cmpf0
> - - const: adtrga0
> - - const: adtrgb0
> - - const: ovf0
> - - const: unf0
> - - const: ccmpa1
> - - const: ccmpb1
> - - const: cmpc1
> - - const: cmpd1
> - - const: cmpe1
> - - const: cmpf1
> - - const: adtrga1
> - - const: adtrgb1
> - - const: ovf1
> - - const: unf1
> - - const: ccmpa2
> - - const: ccmpb2
> - - const: cmpc2
> - - const: cmpd2
> - - const: cmpe2
> - - const: cmpf2
> - - const: adtrga2
> - - const: adtrgb2
> - - const: ovf2
> - - const: unf2
> - - const: ccmpa3
> - - const: ccmpb3
> - - const: cmpc3
> - - const: cmpd3
> - - const: cmpe3
> - - const: cmpf3
> - - const: adtrga3
> - - const: adtrgb3
> - - const: ovf3
> - - const: unf3
> - - const: ccmpa4
> - - const: ccmpb4
> - - const: cmpc4
> - - const: cmpd4
> - - const: cmpe4
> - - const: cmpf4
> - - const: adtrga4
> - - const: adtrgb4
> - - const: ovf4
> - - const: unf4
> - - const: ccmpa5
> - - const: ccmpb5
> - - const: cmpc5
> - - const: cmpd5
> - - const: cmpe5
> - - const: cmpf5
> - - const: adtrga5
> - - const: adtrgb5
> - - const: ovf5
> - - const: unf5
> - - const: ccmpa6
> - - const: ccmpb6
> - - const: cmpc6
> - - const: cmpd6
> - - const: cmpe6
> - - const: cmpf6
> - - const: adtrga6
> - - const: adtrgb6
> - - const: ovf6
> - - const: unf6
> - - const: ccmpa7
> - - const: ccmpb7
> - - const: cmpc7
> - - const: cmpd7
> - - const: cmpe7
> - - const: cmpf7
> - - const: adtrga7
> - - const: adtrgb7
> - - const: ovf7
> - - const: unf7
> + oneOf:
> + - items:
> + - const: ccmpa0
> + - const: ccmpb0
> + - const: cmpc0
> + - const: cmpd0
> + - const: cmpe0
> + - const: cmpf0
> + - const: adtrga0
> + - const: adtrgb0
> + - const: ovf0
> + - const: unf0
> + - const: ccmpa1
> + - const: ccmpb1
> + - const: cmpc1
> + - const: cmpd1
> + - const: cmpe1
> + - const: cmpf1
> + - const: adtrga1
> + - const: adtrgb1
> + - const: ovf1
> + - const: unf1
> + - const: ccmpa2
> + - const: ccmpb2
> + - const: cmpc2
> + - const: cmpd2
> + - const: cmpe2
> + - const: cmpf2
> + - const: adtrga2
> + - const: adtrgb2
> + - const: ovf2
> + - const: unf2
> + - const: ccmpa3
> + - const: ccmpb3
> + - const: cmpc3
> + - const: cmpd3
> + - const: cmpe3
> + - const: cmpf3
> + - const: adtrga3
> + - const: adtrgb3
> + - const: ovf3
> + - const: unf3
> + - const: ccmpa4
> + - const: ccmpb4
> + - const: cmpc4
> + - const: cmpd4
> + - const: cmpe4
> + - const: cmpf4
> + - const: adtrga4
> + - const: adtrgb4
> + - const: ovf4
> + - const: unf4
> + - const: ccmpa5
> + - const: ccmpb5
> + - const: cmpc5
> + - const: cmpd5
> + - const: cmpe5
> + - const: cmpf5
> + - const: adtrga5
> + - const: adtrgb5
> + - const: ovf5
> + - const: unf5
> + - const: ccmpa6
> + - const: ccmpb6
> + - const: cmpc6
> + - const: cmpd6
> + - const: cmpe6
> + - const: cmpf6
> + - const: adtrga6
> + - const: adtrgb6
> + - const: ovf6
> + - const: unf6
> + - const: ccmpa7
> + - const: ccmpb7
> + - const: cmpc7
> + - const: cmpd7
> + - const: cmpe7
> + - const: cmpf7
> + - const: adtrga7
> + - const: adtrgb7
> + - const: ovf7
> + - const: unf7
> + - items:
> + - const: gtcia0
> + - const: gtcib0
> + - const: gtcic0
> + - const: gtcid0
> + - const: gtcie0
> + - const: gtcif0
> + - const: gtcih0
> + - const: gtcil0
> + - const: gtcia1
> + - const: gtcib1
> + - const: gtcic1
> + - const: gtcid1
> + - const: gtcie1
> + - const: gtcif1
> + - const: gtcih1
> + - const: gtcil1
> + - const: gtcia2
> + - const: gtcib2
> + - const: gtcic2
> + - const: gtcid2
> + - const: gtcie2
> + - const: gtcif2
> + - const: gtcih2
> + - const: gtcil2
> + - const: gtcia3
> + - const: gtcib3
> + - const: gtcic3
> + - const: gtcid3
> + - const: gtcie3
> + - const: gtcif3
> + - const: gtcih3
> + - const: gtcil3
> + - const: gtcia4
> + - const: gtcib4
> + - const: gtcic4
> + - const: gtcid4
> + - const: gtcie4
> + - const: gtcif4
> + - const: gtcih4
> + - const: gtcil4
> + - const: gtcia5
> + - const: gtcib5
> + - const: gtcic5
> + - const: gtcid5
> + - const: gtcie5
> + - const: gtcif5
> + - const: gtcih5
> + - const: gtcil5
> + - const: gtcia6
> + - const: gtcib6
> + - const: gtcic6
> + - const: gtcid6
> + - const: gtcie6
> + - const: gtcif6
> + - const: gtcih6
> + - const: gtcil6
> + - const: gtcia7
> + - const: gtcib7
> + - const: gtcic7
> + - const: gtcid7
> + - const: gtcie7
> + - const: gtcif7
> + - const: gtcih7
> + - const: gtcil7
>
> clocks:
> - maxItems: 1
> + items:
> + - description: Core clock (PCLKD)
> + - description: Bus clock (PCLKA)
> + minItems: 1
> +
> + clock-names:
> + items:
> + - const: core
> + - const: bus
>
> power-domains:
> maxItems: 1
>
> resets:
> - maxItems: 1
> + items:
> + - description: Reset for bus clock (PCLKA/PCLKD)
> + - description: Reset for core clock (PCLKD)
> + minItems: 1
> +
> + reset-names:
> + items:
> + - const: rst_p
> + - const: rst_s
>
> required:
> - compatible
> @@ -257,6 +408,42 @@ required:
> allOf:
> - $ref: pwm.yaml#
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a09g047-gpt
> + then:
> + properties:
> + clocks:
> + minItems: 2
> + resets:
> + minItems: 2
> + interrupts:
> + maxItems: 64
> + interrupt-names:
> + maxItems: 64
> +
> + required:
> + - clock-names
> + - reset-names
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,rzg2l-gpt
> + then:
> + properties:
> + clocks:
> + maxItems: 1
> + resets:
> + maxItems: 1
> + interrupts:
> + minItems: 80
> + interrupt-names:
> + minItems: 80
> +
> additionalProperties: false
>
> examples:
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/7] pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip
2025-08-14 18:41 ` [PATCH 2/7] pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip Biju
@ 2025-08-19 16:20 ` Tommaso Merciai
0 siblings, 0 replies; 13+ messages in thread
From: Tommaso Merciai @ 2025-08-19 16:20 UTC (permalink / raw)
To: Biju
Cc: Uwe Kleine-König, Geert Uytterhoeven, Magnus Damm, Biju Das,
linux-pwm, linux-kernel, linux-renesas-soc, Prabhakar Mahadev Lad
Hi Biju,
Thank you for the patch.
On Thu, Aug 14, 2025 at 07:41:06PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> RZ/G3E GPT IP is similar to the one found on RZ/G2L GPT, but there are
> some differences. The field width of prescalar on RZ/G3E is 4 whereas on
> RZ/G2L it is 3. Add rzg2l_gpt_info variable to handle this differences.
> The FIELD_PREP and FIELD_GET macro is giving compilation issue as the
> parameters are not build time constants. So added Non-constant mask
> variant of FIELD_GET() and FIELD_PREP().
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Thanks & Regards,
Tommaso
> ---
> drivers/pwm/pwm-rzg2l-gpt.c | 33 ++++++++++++++++++++++++++++-----
> 1 file changed, 28 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
> index f0a8531457ca..bf989defa527 100644
> --- a/drivers/pwm/pwm-rzg2l-gpt.c
> +++ b/drivers/pwm/pwm-rzg2l-gpt.c
> @@ -33,6 +33,19 @@
> #include <linux/time.h>
> #include <linux/units.h>
>
> +/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
> +#define field_get(_mask, _reg) \
> +({\
> + typeof(_mask) (mask) = (_mask); \
> + (((_reg) & (mask)) >> (ffs(mask) - 1)); \
> +})
> +
> +#define field_prep(_mask, _val) \
> +({\
> + typeof(_mask) (mask) = (_mask); \
> + (((_val) << (ffs(mask) - 1)) & (mask)); \
> +})
> +
> #define RZG2L_GET_CH(hwpwm) ((hwpwm) / 2)
> #define RZG2L_GET_CH_OFFS(ch) (0x100 * (ch))
>
> @@ -46,7 +59,6 @@
>
> #define RZG2L_GTCR_CST BIT(0)
> #define RZG2L_GTCR_MD GENMASK(18, 16)
> -#define RZG2L_GTCR_TPCS GENMASK(26, 24)
>
> #define RZG2L_GTCR_MD_SAW_WAVE_PWM_MODE FIELD_PREP(RZG2L_GTCR_MD, 0)
>
> @@ -77,9 +89,14 @@
> #define RZG2L_MAX_SCALE_FACTOR 1024
> #define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR)
>
> +struct rzg2l_gpt_info {
> + u32 gtcr_tpcs_mask;
> +};
> +
> struct rzg2l_gpt_chip {
> void __iomem *mmio;
> struct mutex lock; /* lock to protect shared channel resources */
> + const struct rzg2l_gpt_info *info;
> unsigned long rate_khz;
> u32 period_ticks[RZG2L_MAX_HW_CHANNELS];
> u32 channel_request_count[RZG2L_MAX_HW_CHANNELS];
> @@ -317,7 +334,7 @@ static int rzg2l_gpt_read_waveform(struct pwm_chip *chip,
>
> if (rzg2l_gpt_is_ch_enabled(rzg2l_gpt, pwm->hwpwm)) {
> gtcr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCR(ch));
> - wfhw->prescale = FIELD_GET(RZG2L_GTCR_TPCS, gtcr);
> + wfhw->prescale = field_get(rzg2l_gpt->info->gtcr_tpcs_mask, gtcr);
> wfhw->gtpr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTPR(ch));
> wfhw->gtccr = rzg2l_gpt_read(rzg2l_gpt, RZG2L_GTCCR(ch, sub_ch));
> if (wfhw->gtccr > wfhw->gtpr)
> @@ -354,8 +371,8 @@ static int rzg2l_gpt_write_waveform(struct pwm_chip *chip,
> rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTUDDTYC(ch), RZG2L_GTUDDTYC_UP_COUNTING);
>
> /* Select count clock */
> - rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), RZG2L_GTCR_TPCS,
> - FIELD_PREP(RZG2L_GTCR_TPCS, wfhw->prescale));
> + rzg2l_gpt_modify(rzg2l_gpt, RZG2L_GTCR(ch), rzg2l_gpt->info->gtcr_tpcs_mask,
> + field_prep(rzg2l_gpt->info->gtcr_tpcs_mask, wfhw->prescale));
>
> /* Set period */
> rzg2l_gpt_write(rzg2l_gpt, RZG2L_GTPR(ch), wfhw->gtpr);
> @@ -414,6 +431,8 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
> if (IS_ERR(rzg2l_gpt->mmio))
> return PTR_ERR(rzg2l_gpt->mmio);
>
> + rzg2l_gpt->info = of_device_get_match_data(dev);
> +
> rstc = devm_reset_control_get_exclusive_deasserted(dev, NULL);
> if (IS_ERR(rstc))
> return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\n");
> @@ -456,8 +475,12 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
> return 0;
> }
>
> +static const struct rzg2l_gpt_info rzg2l_data = {
> + .gtcr_tpcs_mask = GENMASK(26, 24),
> +};
> +
> static const struct of_device_id rzg2l_gpt_of_table[] = {
> - { .compatible = "renesas,rzg2l-gpt", },
> + { .compatible = "renesas,rzg2l-gpt", .data = &rzg2l_data },
> { /* Sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, rzg2l_gpt_of_table);
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 3/7] pwm: rzg2l-gpt: Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info
2025-08-14 18:41 ` [PATCH 3/7] pwm: rzg2l-gpt: Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info Biju
@ 2025-08-19 16:21 ` Tommaso Merciai
0 siblings, 0 replies; 13+ messages in thread
From: Tommaso Merciai @ 2025-08-19 16:21 UTC (permalink / raw)
To: Biju
Cc: Uwe Kleine-König, Geert Uytterhoeven, Magnus Damm, Biju Das,
linux-pwm, linux-kernel, linux-renesas-soc, Prabhakar Mahadev Lad
Hi Biju,
Thank you for your patch.
On Thu, Aug 14, 2025 at 07:41:07PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> RZ/G3E GPT IP has prescale factor power of 2 where as that of RZ/G2L is 4.
> Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info for
> handling this difference.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Thanks & Regards,
Tommaso
> ---
> drivers/pwm/pwm-rzg2l-gpt.c | 17 ++++++++++++-----
> 1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
> index bf989defa527..74bb0cca4ab4 100644
> --- a/drivers/pwm/pwm-rzg2l-gpt.c
> +++ b/drivers/pwm/pwm-rzg2l-gpt.c
> @@ -91,6 +91,7 @@
>
> struct rzg2l_gpt_info {
> u32 gtcr_tpcs_mask;
> + u8 prescale_pow_of_two_mult_factor;
> };
>
> struct rzg2l_gpt_chip {
> @@ -226,6 +227,7 @@ static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *rzg2l_gpt,
> static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,
> u32 val, u8 prescale)
> {
> + const struct rzg2l_gpt_info *info = rzg2l_gpt->info;
> u64 tmp;
>
> /*
> @@ -235,15 +237,18 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt,
> * < 2^32 * 2^10 * 2^20
> * = 2^62
> */
> - tmp = (u64)val << (2 * prescale);
> + tmp = (u64)val << (info->prescale_pow_of_two_mult_factor * prescale);
> tmp *= USEC_PER_SEC;
>
> return DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz);
> }
>
> -static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 prescale)
> +static u32 rzg2l_gpt_calculate_pv_or_dc(const struct rzg2l_gpt_info *info,
> + u64 period_or_duty_cycle, u8 prescale)
> {
> - return min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * prescale)),
> + return min_t(u64,
> + DIV_ROUND_DOWN_ULL(period_or_duty_cycle,
> + 1 << (info->prescale_pow_of_two_mult_factor * prescale)),
> U32_MAX);
> }
>
> @@ -254,6 +259,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,
>
> {
> struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
> + const struct rzg2l_gpt_info *info = rzg2l_gpt->info;
> struct rzg2l_gpt_waveform *wfhw = _wfhw;
> u8 ch = RZG2L_GET_CH(pwm->hwpwm);
> u64 period_ticks, duty_ticks;
> @@ -287,12 +293,12 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,
> }
>
> wfhw->prescale = rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks);
> - pv = rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale);
> + pv = rzg2l_gpt_calculate_pv_or_dc(info, period_ticks, wfhw->prescale);
> wfhw->gtpr = pv;
> duty_ticks = mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_khz, USEC_PER_SEC);
> if (duty_ticks > period_ticks)
> duty_ticks = period_ticks;
> - dc = rzg2l_gpt_calculate_pv_or_dc(duty_ticks, wfhw->prescale);
> + dc = rzg2l_gpt_calculate_pv_or_dc(info, duty_ticks, wfhw->prescale);
> wfhw->gtccr = dc;
>
> /*
> @@ -477,6 +483,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
>
> static const struct rzg2l_gpt_info rzg2l_data = {
> .gtcr_tpcs_mask = GENMASK(26, 24),
> + .prescale_pow_of_two_mult_factor = 2,
> };
>
> static const struct of_device_id rzg2l_gpt_of_table[] = {
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 4/7] pwm: rzg2l-gpt: Add calculate_prescale() callback to struct rzg2l_gpt_info
2025-08-14 18:41 ` [PATCH 4/7] pwm: rzg2l-gpt: Add calculate_prescale() callback " Biju
@ 2025-08-19 16:22 ` Tommaso Merciai
0 siblings, 0 replies; 13+ messages in thread
From: Tommaso Merciai @ 2025-08-19 16:22 UTC (permalink / raw)
To: Biju
Cc: Uwe Kleine-König, Geert Uytterhoeven, Magnus Damm, Biju Das,
linux-pwm, linux-kernel, linux-renesas-soc, Prabhakar Mahadev Lad
Hi Biju,
Thank you for your patch.
On Thu, Aug 14, 2025 at 07:41:08PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> RZ/G2L GPT the prescale factors are continuous power of 4 whereas on RZ/G3E
> it is power of 2 but discontinuous. Add calculate_prescale() callback to
> struct rzg2l_gpt_info for handling this difference.
>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Thanks & Regards,
Tommaso
> ---
> drivers/pwm/pwm-rzg2l-gpt.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
> index 74bb0cca4ab4..b247a6c181d5 100644
> --- a/drivers/pwm/pwm-rzg2l-gpt.c
> +++ b/drivers/pwm/pwm-rzg2l-gpt.c
> @@ -90,6 +90,7 @@
> #define RZG2L_MAX_TICKS ((u64)U32_MAX * RZG2L_MAX_SCALE_FACTOR)
>
> struct rzg2l_gpt_info {
> + u8 (*calculate_prescale)(u64 period);
> u32 gtcr_tpcs_mask;
> u8 prescale_pow_of_two_mult_factor;
> };
> @@ -138,8 +139,7 @@ static void rzg2l_gpt_modify(struct rzg2l_gpt_chip *rzg2l_gpt, u32 reg, u32 clr,
> (rzg2l_gpt_read(rzg2l_gpt, reg) & ~clr) | set);
> }
>
> -static u8 rzg2l_gpt_calculate_prescale(struct rzg2l_gpt_chip *rzg2l_gpt,
> - u64 period_ticks)
> +static u8 rzg2l_gpt_calculate_prescale(u64 period_ticks)
> {
> u32 prescaled_period_ticks;
> u8 prescale;
> @@ -292,7 +292,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_chip *chip,
> period_ticks = rzg2l_gpt->period_ticks[ch];
> }
>
> - wfhw->prescale = rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks);
> + wfhw->prescale = info->calculate_prescale(period_ticks);
> pv = rzg2l_gpt_calculate_pv_or_dc(info, period_ticks, wfhw->prescale);
> wfhw->gtpr = pv;
> duty_ticks = mul_u64_u64_div_u64(wf->duty_length_ns, rzg2l_gpt->rate_khz, USEC_PER_SEC);
> @@ -482,6 +482,7 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
> }
>
> static const struct rzg2l_gpt_info rzg2l_data = {
> + .calculate_prescale = rzg2l_gpt_calculate_prescale,
> .gtcr_tpcs_mask = GENMASK(26, 24),
> .prescale_pow_of_two_mult_factor = 2,
> };
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 5/7] pwm: rzg2l-gpt: Add RZ/G3E support
2025-08-14 18:41 ` [PATCH 5/7] pwm: rzg2l-gpt: Add RZ/G3E support Biju
@ 2025-08-19 16:23 ` Tommaso Merciai
0 siblings, 0 replies; 13+ messages in thread
From: Tommaso Merciai @ 2025-08-19 16:23 UTC (permalink / raw)
To: Biju
Cc: Uwe Kleine-König, Geert Uytterhoeven, Magnus Damm, Biju Das,
linux-pwm, linux-kernel, linux-renesas-soc, Prabhakar Mahadev Lad
Hi Biju,
Thank you for your patch.
On Thu, Aug 14, 2025 at 07:41:09PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add RZ/G3E GPT support. It has multiple clocks and resets compared to
> RZ/G2L. Also prescale field width and factor for calculating prescale
> are different.
>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> drivers/pwm/pwm-rzg2l-gpt.c | 36 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c
> index b247a6c181d5..7047359cac63 100644
> --- a/drivers/pwm/pwm-rzg2l-gpt.c
> +++ b/drivers/pwm/pwm-rzg2l-gpt.c
> @@ -153,6 +153,27 @@ static u8 rzg2l_gpt_calculate_prescale(u64 period_ticks)
> return prescale;
> }
>
> +static u8 rzg3e_gpt_calculate_prescale(u64 period_ticks)
> +{
> + u32 prescaled_period_ticks;
> + u8 prescale;
> +
> + prescaled_period_ticks = period_ticks >> 32;
> + if (prescaled_period_ticks >= 64 && prescaled_period_ticks < 256) {
> + prescale = 6;
> + } else if (prescaled_period_ticks >= 256 && prescaled_period_ticks < 1024) {
> + prescale = 8;
> + } else if (prescaled_period_ticks >= 1024) {
> + prescale = 10;
> + } else {
> + prescale = fls(prescaled_period_ticks);
> + if (prescale > 1)
> + prescale -= 1;
> + }
> +
> + return prescale;
> +}
> +
> static int rzg2l_gpt_request(struct pwm_chip *chip, struct pwm_device *pwm)
> {
> struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip);
> @@ -443,6 +464,14 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
> if (IS_ERR(rstc))
> return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\n");
>
> + rstc = devm_reset_control_get_optional_exclusive_deasserted(dev, "rst_s");
> + if (IS_ERR(rstc))
> + return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert rst_s reset\n");
> +
> + clk = devm_clk_get_optional_enabled(dev, "bus");
> + if (IS_ERR(clk))
> + return dev_err_probe(dev, PTR_ERR(clk), "Cannot get bus clock\n");
> +
> clk = devm_clk_get_enabled(dev, NULL);
> if (IS_ERR(clk))
> return dev_err_probe(dev, PTR_ERR(clk), "Cannot get clock\n");
> @@ -481,6 +510,12 @@ static int rzg2l_gpt_probe(struct platform_device *pdev)
> return 0;
> }
>
> +static const struct rzg2l_gpt_info rzg3e_data = {
> + .calculate_prescale = rzg3e_gpt_calculate_prescale,
> + .gtcr_tpcs_mask = GENMASK(26, 23),
> + .prescale_pow_of_two_mult_factor = 1,
> +};
> +
> static const struct rzg2l_gpt_info rzg2l_data = {
> .calculate_prescale = rzg2l_gpt_calculate_prescale,
> .gtcr_tpcs_mask = GENMASK(26, 24),
> @@ -488,6 +523,7 @@ static const struct rzg2l_gpt_info rzg2l_data = {
> };
>
> static const struct of_device_id rzg2l_gpt_of_table[] = {
> + { .compatible = "renesas,r9a09g047-gpt", .data = &rzg3e_data },
> { .compatible = "renesas,rzg2l-gpt", .data = &rzg2l_data },
> { /* Sentinel */ }
> };
> --
> 2.43.0
>
Thanks & Regards,
Tommaso
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document RZ/G3E support
2025-08-14 18:41 ` [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document " Biju
2025-08-19 16:18 ` Tommaso Merciai
@ 2025-08-20 20:29 ` Rob Herring
2025-08-21 7:04 ` Biju Das
1 sibling, 1 reply; 13+ messages in thread
From: Rob Herring @ 2025-08-20 20:29 UTC (permalink / raw)
To: Biju
Cc: Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Biju Das, linux-pwm, devicetree,
linux-kernel, linux-renesas-soc, Prabhakar Mahadev Lad
On Thu, Aug 14, 2025 at 07:41:05PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document support for the GPT found on the Renesas RZ/G3E (R9A09G047)
> SoC.
>
> The GPT IP on these parts is similar to that on RZ/G2L but supports
> only 8 interrupts per channel and has multiple clocks and resets.
> Introduce a new compatible string `renesas,r9a09g047-gpt` for RZ/G3E.
Doesn't look like a lot in common to me. I think this should be a
separate document.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> .../bindings/pwm/renesas,rzg2l-gpt.yaml | 525 ++++++++++++------
> 1 file changed, 356 insertions(+), 169 deletions(-)
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document RZ/G3E support
2025-08-20 20:29 ` Rob Herring
@ 2025-08-21 7:04 ` Biju Das
0 siblings, 0 replies; 13+ messages in thread
From: Biju Das @ 2025-08-21 7:04 UTC (permalink / raw)
To: Rob Herring, biju.das.au
Cc: Uwe Kleine-König, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, magnus.damm, linux-pwm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad
Hi Rob,
Thanks for the feedback.
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 20 August 2025 21:29
> Subject: Re: [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document RZ/G3E support
>
> On Thu, Aug 14, 2025 at 07:41:05PM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Document support for the GPT found on the Renesas RZ/G3E (R9A09G047)
> > SoC.
> >
> > The GPT IP on these parts is similar to that on RZ/G2L but supports
> > only 8 interrupts per channel and has multiple clocks and resets.
> > Introduce a new compatible string `renesas,r9a09g047-gpt` for RZ/G3E.
>
> Doesn't look like a lot in common to me. I think this should be a separate document.
OK, I will describe it in a separate document.
Cheers,
Biju
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2025-08-21 7:04 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-08-14 18:41 [PATCH 0/7] Add RZ/G3E support Biju
2025-08-14 18:41 ` [PATCH 1/7] dt-bindings: pwm: renesas,rzg2l-gpt: Document " Biju
2025-08-19 16:18 ` Tommaso Merciai
2025-08-20 20:29 ` Rob Herring
2025-08-21 7:04 ` Biju Das
2025-08-14 18:41 ` [PATCH 2/7] pwm: rzg2l-gpt: Add info variable to struct rzg2l_gpt_chip Biju
2025-08-19 16:20 ` Tommaso Merciai
2025-08-14 18:41 ` [PATCH 3/7] pwm: rzg2l-gpt: Add prescale_pow_of_two_mult_factor variable to struct rzg2l_gpt_info Biju
2025-08-19 16:21 ` Tommaso Merciai
2025-08-14 18:41 ` [PATCH 4/7] pwm: rzg2l-gpt: Add calculate_prescale() callback " Biju
2025-08-19 16:22 ` Tommaso Merciai
2025-08-14 18:41 ` [PATCH 5/7] pwm: rzg2l-gpt: Add RZ/G3E support Biju
2025-08-19 16:23 ` Tommaso Merciai
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