[PATCH 0/2] pwm: mediatek: fix mt7628 register offset and clock source

[PATCH 0/2] pwm: mediatek: fix mt7628 register offset and clock source

[Shiji Yang]

This patch series fixes support for mt7628.

Shiji Yang (2):
  pwm: mediatek: set mt7628 pwm45_fixup flag to false
  pwm: mediatek: correct mt7628 clock source setting

 drivers/pwm/pwm-mediatek.c | 25 +++++++++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

-- 
2.51.0

[PATCH 1/2] pwm: mediatek: set mt7628 pwm45_fixup flag to false

[Shiji Yang]

According to the programing guide, mt7628 has generic register layout
like most other hardware revisions. We should not set pwm45_fixup flag
for it.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
---
 drivers/pwm/pwm-mediatek.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index 9d2063034..dee61e7ca 100644
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -525,7 +525,7 @@ static const struct pwm_mediatek_of_data mt7623_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt7628_pwm_data = {
 	.num_pwms = 4,
-	.pwm45_fixup = true,
+	.pwm45_fixup = false,
 	.chanreg_base = 0x10,
 	.chanreg_width = 0x40,
 };
-- 
2.51.0

[PATCH 2/2] pwm: mediatek: correct mt7628 clock source setting

[Shiji Yang]

PWMCON register Bit(3) is used to configure whether to pre divide
the clock source. Most revisions clear this bit to disable frequency
division. However, mt7628 needs to set this bit. Hence, we introduce
a new clksel_fixup flag to correctly configure the clock source for
mt7628.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
---
 drivers/pwm/pwm-mediatek.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
index dee61e7ca..992137a27 100644
--- a/drivers/pwm/pwm-mediatek.c
+++ b/drivers/pwm/pwm-mediatek.c
@@ -23,6 +23,8 @@
 /* PWM registers and bits definitions */
 #define PWMCON			0x00
 #define PWMCON_CLKDIV			GENMASK(2, 0)
+#define PWMCON_CLKSEL			BIT(3)
+#define PWMCON_OLD_PWM_MODE		BIT(15)
 #define PWMHDUR			0x04
 #define PWMLDUR			0x08
 #define PWMGDUR			0x0c
@@ -38,6 +40,7 @@
 
 struct pwm_mediatek_of_data {
 	unsigned int num_pwms;
+	bool clksel_fixup;
 	bool pwm45_fixup;
 	u16 pwm_ck_26m_sel_reg;
 	unsigned int chanreg_base;
@@ -337,6 +340,7 @@ static int pwm_mediatek_write_waveform(struct pwm_chip *chip,
 
 	if (wfhw->enable) {
 		u32 reg_width = PWMDWIDTH, reg_thres = PWMTHRES;
+		u32 con_val = PWMCON_OLD_PWM_MODE | wfhw->con;
 
 		if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
 			/*
@@ -364,7 +368,11 @@ static int pwm_mediatek_write_waveform(struct pwm_chip *chip,
 		if (pc->soc->pwm_ck_26m_sel_reg)
 			writel(0, pc->regs + pc->soc->pwm_ck_26m_sel_reg);
 
-		pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | wfhw->con);
+		/* Set BIT(3) to disable clock division */
+		if (pc->soc->clksel_fixup)
+			con_val |= PWMCON_CLKSEL;
+
+		pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, con_val);
 		pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, wfhw->width);
 		pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, wfhw->thres);
 	} else {
@@ -496,6 +504,7 @@ static int pwm_mediatek_probe(struct platform_device *pdev)
 
 static const struct pwm_mediatek_of_data mt2712_pwm_data = {
 	.num_pwms = 8,
+	.clksel_fixup = false,
 	.pwm45_fixup = false,
 	.chanreg_base = 0x10,
 	.chanreg_width = 0x40,
@@ -503,6 +512,7 @@ static const struct pwm_mediatek_of_data mt2712_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt6795_pwm_data = {
 	.num_pwms = 7,
+	.clksel_fixup = false,
 	.pwm45_fixup = false,
 	.chanreg_base = 0x10,
 	.chanreg_width = 0x40,
@@ -510,6 +520,7 @@ static const struct pwm_mediatek_of_data mt6795_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt7622_pwm_data = {
 	.num_pwms = 6,
+	.clksel_fixup = false,
 	.pwm45_fixup = false,
 	.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
 	.chanreg_base = 0x10,
@@ -518,6 +529,7 @@ static const struct pwm_mediatek_of_data mt7622_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt7623_pwm_data = {
 	.num_pwms = 5,
+	.clksel_fixup = false,
 	.pwm45_fixup = true,
 	.chanreg_base = 0x10,
 	.chanreg_width = 0x40,
@@ -525,6 +537,7 @@ static const struct pwm_mediatek_of_data mt7623_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt7628_pwm_data = {
 	.num_pwms = 4,
+	.clksel_fixup = true,
 	.pwm45_fixup = false,
 	.chanreg_base = 0x10,
 	.chanreg_width = 0x40,
@@ -532,6 +545,7 @@ static const struct pwm_mediatek_of_data mt7628_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt7629_pwm_data = {
 	.num_pwms = 1,
+	.clksel_fixup = false,
 	.pwm45_fixup = false,
 	.chanreg_base = 0x10,
 	.chanreg_width = 0x40,
@@ -539,6 +553,7 @@ static const struct pwm_mediatek_of_data mt7629_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt7981_pwm_data = {
 	.num_pwms = 3,
+	.clksel_fixup = false,
 	.pwm45_fixup = false,
 	.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
 	.chanreg_base = 0x80,
@@ -547,6 +562,7 @@ static const struct pwm_mediatek_of_data mt7981_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt7986_pwm_data = {
 	.num_pwms = 2,
+	.clksel_fixup = false,
 	.pwm45_fixup = false,
 	.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
 	.chanreg_base = 0x10,
@@ -555,6 +571,7 @@ static const struct pwm_mediatek_of_data mt7986_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt7988_pwm_data = {
 	.num_pwms = 8,
+	.clksel_fixup = false,
 	.pwm45_fixup = false,
 	.chanreg_base = 0x80,
 	.chanreg_width = 0x40,
@@ -562,6 +579,7 @@ static const struct pwm_mediatek_of_data mt7988_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt8183_pwm_data = {
 	.num_pwms = 4,
+	.clksel_fixup = false,
 	.pwm45_fixup = false,
 	.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
 	.chanreg_base = 0x10,
@@ -570,6 +588,7 @@ static const struct pwm_mediatek_of_data mt8183_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt8365_pwm_data = {
 	.num_pwms = 3,
+	.clksel_fixup = false,
 	.pwm45_fixup = false,
 	.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
 	.chanreg_base = 0x10,
@@ -578,6 +597,7 @@ static const struct pwm_mediatek_of_data mt8365_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt8516_pwm_data = {
 	.num_pwms = 5,
+	.clksel_fixup = false,
 	.pwm45_fixup = false,
 	.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL,
 	.chanreg_base = 0x10,
@@ -586,6 +606,7 @@ static const struct pwm_mediatek_of_data mt8516_pwm_data = {
 
 static const struct pwm_mediatek_of_data mt6991_pwm_data = {
 	.num_pwms = 4,
+	.clksel_fixup = false,
 	.pwm45_fixup = false,
 	.pwm_ck_26m_sel_reg = PWM_CK_26M_SEL_V3,
 	.chanreg_base = 0x100,
-- 
2.51.0

Re: [PATCH 0/2] pwm: mediatek: fix mt7628 register offset and clock source

[Uwe Kleine-König]

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Hello,

On Tue, Feb 24, 2026 at 04:51:00PM +0800, Shiji Yang wrote:
> This patch series fixes support for mt7628.

The series looks reasonable to me. It would be great to get some
feedback from the Mediatek maintainers, though?!

Best regards
Uwe

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