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[93.5.22.158]) by smtp.gmail.com with ESMTPSA id s12-20020adfeccc000000b002da1261aa44sm14576762wro.48.2023.04.05.02.26.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Apr 2023 02:26:31 -0700 (PDT) Message-ID: Date: Wed, 5 Apr 2023 11:26:30 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.9.0 Subject: Re: [PATCH RESEND 1/2] pwm: mtk-disp: Disable shadow registers before setting backlight values Content-Language: en-US To: AngeloGioacchino Del Regno , thierry.reding@gmail.com Cc: u.kleine-koenig@pengutronix.de, matthias.bgg@gmail.com, weiqing.kong@mediatek.com, jitao.shi@mediatek.com, linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, wenst@chromium.org, =?UTF-8?Q?N=c3=adcolas_F_=2e_R_=2e_A_=2e_Prado?= References: <20230403133054.319070-1-angelogioacchino.delregno@collabora.com> <20230403133054.319070-2-angelogioacchino.delregno@collabora.com> From: Alexandre Mergnat In-Reply-To: <20230403133054.319070-2-angelogioacchino.delregno@collabora.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org On 03/04/2023 15:30, AngeloGioacchino Del Regno wrote: > If shadow registers usage is not desired, disable that before performing > any write to CON0/1 registers in the .apply() callback, otherwise we may > lose clkdiv or period/width updates. > > Fixes: cd4b45ac449a ("pwm: Add MediaTek MT2701 display PWM driver support") > Signed-off-by: AngeloGioacchino Del Regno > Reviewed-by: Nícolas F. R. A. Prado > Tested-by: Nícolas F. R. A. Prado > --- > drivers/pwm/pwm-mtk-disp.c | 24 +++++++++++++----------- > 1 file changed, 13 insertions(+), 11 deletions(-) > > diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c > index 692a06121b28..82b430d881a2 100644 > --- a/drivers/pwm/pwm-mtk-disp.c > +++ b/drivers/pwm/pwm-mtk-disp.c > @@ -138,6 +138,19 @@ static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > high_width = mul_u64_u64_div_u64(state->duty_cycle, rate, div); > value = period | (high_width << PWM_HIGH_WIDTH_SHIFT); > > + if (mdp->data->bls_debug && !mdp->data->has_commit) { > + /* > + * For MT2701, disable double buffer before writing register > + * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH. > + */ > + mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug, > + mdp->data->bls_debug_mask, > + mdp->data->bls_debug_mask); > + mtk_disp_pwm_update_bits(mdp, mdp->data->con0, > + mdp->data->con0_sel, > + mdp->data->con0_sel); > + } > + > mtk_disp_pwm_update_bits(mdp, mdp->data->con0, > PWM_CLKDIV_MASK, > clk_div << PWM_CLKDIV_SHIFT); > @@ -152,17 +165,6 @@ static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > mtk_disp_pwm_update_bits(mdp, mdp->data->commit, > mdp->data->commit_mask, > 0x0); > - } else { > - /* > - * For MT2701, disable double buffer before writing register > - * and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH. > - */ > - mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug, > - mdp->data->bls_debug_mask, > - mdp->data->bls_debug_mask); > - mtk_disp_pwm_update_bits(mdp, mdp->data->con0, > - mdp->data->con0_sel, > - mdp->data->con0_sel); > } > > mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, Hi, I've made a non-regression test for the mt8365-evk (i350-evk) board. It's fine for me. Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat Regards, Alex