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From: David Laight <david.laight.linux@gmail.com>
To: Christoph Hellwig <hch@infradead.org>
Cc: Eric Biggers <ebiggers@kernel.org>,
	x86@kernel.org, linux-kernel@vger.kernel.org,
	linux-raid@vger.kernel.org, linux-crypto@vger.kernel.org,
	Herbert Xu <herbert@gondor.apana.org.au>,
	Taehee Yoo <ap420073@gmail.com>,
	netfilter-devel@vger.kernel.org,
	Pablo Neira Ayuso <pablo@netfilter.org>,
	Florian Westphal <fw@strlen.de>, Phil Sutter <phil@nwl.cc>
Subject: Re: [PATCH 0/6] x86: add missing vzeroupper instructions
Date: Mon, 17 Aug 2026 11:55:23 +0100	[thread overview]
Message-ID: <20260817115523.7c6c646a@pumpkin> (raw)
In-Reply-To: <aoLRJ7igR5GTMfuO@infradead.org>

On Mon, 17 Aug 2026 02:15:19 -0700
Christoph Hellwig <hch@infradead.org> wrote:

> On Sun, Aug 16, 2026 at 10:31:59AM -0700, Eric Biggers wrote:
> > As for kernel_fpu_begin(), no, it doesn't do vzeroupper.
> > 
> > I do think that some years down the line, we'll drop the use of SSE in
> > the kernel entirely.  At that point, vzeroupper in kernel_fpu_end()
> > would make sense.  
> 
> Or add kernel_avx_{begin,end} wrappers that include the vzeroupper
> in kernel_avx_end.  That would be a lot easier to use than the manual
> vzeroupper in every modern user of in-kernel AVX.
> 

You might want one in the start as well.
I have a theory that the avx512 logic was added as a completely separate block.
This meant it could be included in cpu for testing but disabled in any
released to customers.
(Or maybe the it is the original avx logic that used latches not in the
normal register file.)
A side effect is that different latches are used for the low bits of the
registers - so when you change to/from avx512 the register contents have to
be transferred between the blocks - adding latency.
So if the wrong registers are live for the code you are going to execute
the data has to be transferred across.

There are also other effects as well.
I found this link: https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html
It is a few years old now (2020) but probably still relevant.
A quick summary is that the first 256 or 512 bit instruction starts a 9us
window where the cpu runs at 1/4 speed, for 512 bit that is followed by 11us
where nothing happens at all. 

	David

  reply	other threads:[~2026-08-17 10:55 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-15 20:57 [PATCH 0/6] x86: add missing vzeroupper instructions Eric Biggers
2026-08-15 20:57 ` [PATCH 1/6] xor: add missing vzeroupper to AVX code Eric Biggers
2026-08-15 20:57 ` [PATCH 2/6] raid6: add missing vzeroupper to AVX2 code Eric Biggers
2026-08-15 21:07   ` sashiko-bot
2026-08-15 20:57 ` [PATCH 3/6] raid6: add missing vzeroupper to AVX-512 code Eric Biggers
2026-08-15 21:06   ` sashiko-bot
2026-08-15 20:57 ` [PATCH 4/6] crypto: x86/aria - add missing vzeroupper in AVX2 code Eric Biggers
2026-08-15 21:08   ` sashiko-bot
2026-08-15 20:57 ` [PATCH 5/6] crypto: x86/aria - add missing vzeroupper in AVX-512 code Eric Biggers
2026-08-15 20:57 ` [PATCH 6/6] netfilter: nft_set_pipapo_avx2: add missing vzeroupper Eric Biggers
2026-08-16 10:38   ` Stefano Brivio
2026-08-16 17:15     ` Eric Biggers
2026-08-17 11:17       ` Stefano Brivio
2026-08-17 11:17   ` Stefano Brivio
2026-08-16 15:14 ` [PATCH 0/6] x86: add missing vzeroupper instructions David Laight
2026-08-16 17:31   ` Eric Biggers
2026-08-17  9:15     ` Christoph Hellwig
2026-08-17 10:55       ` David Laight [this message]
2026-08-17 17:18         ` Eric Biggers

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