From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A68BFC433E0 for ; Sun, 7 Feb 2021 08:16:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6AD4C64EA4 for ; Sun, 7 Feb 2021 08:16:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229510AbhBGIPz convert rfc822-to-8bit (ORCPT ); Sun, 7 Feb 2021 03:15:55 -0500 Received: from szxga01-in.huawei.com ([45.249.212.187]:4611 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229445AbhBGIPx (ORCPT ); Sun, 7 Feb 2021 03:15:53 -0500 Received: from DGGEMM404-HUB.china.huawei.com (unknown [172.30.72.54]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4DYMPJ3fZlzY6XJ; Sun, 7 Feb 2021 16:13:56 +0800 (CST) Received: from dggema704-chm.china.huawei.com (10.3.20.68) by DGGEMM404-HUB.china.huawei.com (10.3.20.212) with Microsoft SMTP Server (TLS) id 14.3.498.0; Sun, 7 Feb 2021 16:15:10 +0800 Received: from dggema753-chm.china.huawei.com (10.1.198.195) by dggema704-chm.china.huawei.com (10.3.20.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2106.2; Sun, 7 Feb 2021 16:15:09 +0800 Received: from dggema753-chm.china.huawei.com ([10.9.48.84]) by dggema753-chm.china.huawei.com ([10.9.48.84]) with mapi id 15.01.2106.006; Sun, 7 Feb 2021 16:15:09 +0800 From: liweihang To: chenglang , "dledford@redhat.com" , "jgg@nvidia.com" CC: "leon@kernel.org" , "linux-rdma@vger.kernel.org" , "linuxarm@openeuler.org" Subject: Re: [PATCH for-next 2/6] RDMA/hns: Remove unsupported CMDQ mode Thread-Topic: [PATCH for-next 2/6] RDMA/hns: Remove unsupported CMDQ mode Thread-Index: AQHW+r6puHaBl39fEkSLE9sC8gGRfg== Date: Sun, 7 Feb 2021 08:15:09 +0000 Message-ID: <11e5e5424ad94e329c11e7a7a77f585e@huawei.com> References: <1612419786-39173-1-git-send-email-liweihang@huawei.com> <1612419786-39173-3-git-send-email-liweihang@huawei.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.67.100.165] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org On 2021/2/7 15:52, chenglang wrote: > > On 2021/2/4 14:23, Weihang Li wrote: >> From: Lang Cheng >> >> HIP08/09 only supports CMDQ in non-interrupt mode, and the firmware always >> ignores the flag to indicate the mode. Therefore, remove the dead code. >> >> Fixes: a04ff739f2a9 ("RDMA/hns: Add command queue support for hip08 RoCE driver") >> Signed-off-by: Lang Cheng >> Signed-off-by: Weihang Li >> --- >> drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 24 ++++++++---------------- >> drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 2 -- >> 2 files changed, 8 insertions(+), 18 deletions(-) >> >> diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c >> index 7a5a41d..260c17c 100644 >> --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c >> +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c >> @@ -1197,8 +1197,7 @@ static void hns_roce_cmq_setup_basic_desc(struct hns_roce_cmq_desc *desc, >> { >> memset((void *)desc, 0, sizeof(struct hns_roce_cmq_desc)); >> desc->opcode = cpu_to_le16(opcode); >> - desc->flag = >> - cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN); >> + desc->flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); >> if (is_read) >> desc->flag |= cpu_to_le16(HNS_ROCE_CMD_FLAG_WR); >> else >> @@ -1275,18 +1274,12 @@ static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, >> /* Write to hardware */ >> roce_write(hr_dev, ROCEE_TX_CMQ_TAIL_REG, csq->next_to_use); >> >> - /* >> - * If the command is sync, wait for the firmware to write back, >> - * if multi descriptors to be sent, use the first one to check >> - */ >> - if (le16_to_cpu(desc->flag) & HNS_ROCE_CMD_FLAG_NO_INTR) { >> - do { >> - if (hns_roce_cmq_csq_done(hr_dev)) >> - break; >> - udelay(1); >> - timeout++; >> - } while (timeout < priv->cmq.tx_timeout); >> - } >> + do { >> + if (hns_roce_cmq_csq_done(hr_dev)) >> + break; >> + udelay(1); >> + timeout++; >> + } while (timeout < priv->cmq.tx_timeout); >> >> if (hns_roce_cmq_csq_done(hr_dev)) { >> handle = 0; >> @@ -1626,8 +1619,7 @@ static int hns_roce_set_vf_switch_param(struct hns_roce_dev *hr_dev, int vf_id) >> if (ret) >> return ret; >> >> - desc.flag = >> - cpu_to_le16(HNS_ROCE_CMD_FLAG_NO_INTR | HNS_ROCE_CMD_FLAG_IN); > > The old firmware needs this redundant flag, it is best cleaned up after the > firmware version is released. > > Thanks. Got it, I will drop this one from the series. Thanks Weihang > >> + desc.flag = cpu_to_le16(HNS_ROCE_CMD_FLAG_IN); >> desc.flag &= cpu_to_le16(~HNS_ROCE_CMD_FLAG_WR); >> roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LPBK_S, 1); >> roce_set_bit(swt->cfg, VF_SWITCH_DATA_CFG_ALW_LCL_LPBK_S, 0); >> diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h >> index 9f97e32..986a287 100644 >> --- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h >> +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h >> @@ -128,14 +128,12 @@ >> #define HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT 1 >> #define HNS_ROCE_CMD_FLAG_NEXT_SHIFT 2 >> #define HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT 3 >> -#define HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT 4 >> #define HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT 5 >> >> #define HNS_ROCE_CMD_FLAG_IN BIT(HNS_ROCE_CMD_FLAG_IN_VALID_SHIFT) >> #define HNS_ROCE_CMD_FLAG_OUT BIT(HNS_ROCE_CMD_FLAG_OUT_VALID_SHIFT) >> #define HNS_ROCE_CMD_FLAG_NEXT BIT(HNS_ROCE_CMD_FLAG_NEXT_SHIFT) >> #define HNS_ROCE_CMD_FLAG_WR BIT(HNS_ROCE_CMD_FLAG_WR_OR_RD_SHIFT) >> -#define HNS_ROCE_CMD_FLAG_NO_INTR BIT(HNS_ROCE_CMD_FLAG_NO_INTR_SHIFT) >> #define HNS_ROCE_CMD_FLAG_ERR_INTR BIT(HNS_ROCE_CMD_FLAG_ERR_INTR_SHIFT) >> >> #define HNS_ROCE_CMQ_DESC_NUM_S 3