[PATCH for-next 0/4] Misc. fixes and cleanup for iw_cxgb4

[PATCH for-next 0/4] Misc. fixes and cleanup for iw_cxgb4

[Hariprasad Shenai]

Hi,

This patch series changes a macro definition to be consistent with other
register macro defines. Fixes for 32b platform, use BAR2 register for kernel
mode CQ's and enforces qp/cq id requirements.

The patches series is created against 'infiniband' tree for-next branch.
And includes patches on iw_cxgb4 driver.

We have included all the maintainers of respective drivers. Kindly review the
change and let us know in case of any review comments.

Thanks

Hariprasad Shenai (4):
  iw_cxgb4: Cleanup register defines/MACROS
  iw_cxgb4: 32b platform fixes
  iw_cxgb4: use BAR2 GTS register for T5 kernel mode CQs
  iw_cxgb4: enforce qp/cq id requirements

 drivers/infiniband/hw/cxgb4/cm.c          |    6 +++---
 drivers/infiniband/hw/cxgb4/cq.c          |   21 ++++++++++++++-------
 drivers/infiniband/hw/cxgb4/device.c      |   29 ++++++++++++++++++++++++++---
 drivers/infiniband/hw/cxgb4/mem.c         |   10 +++++-----
 drivers/infiniband/hw/cxgb4/qp.c          |   14 +++++++-------
 drivers/infiniband/hw/cxgb4/t4.h          |    7 ++++---
 drivers/infiniband/hw/cxgb4/t4fw_ri_api.h |    4 +++-
 7 files changed, 62 insertions(+), 29 deletions(-)

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[PATCH for-next 1/4] iw_cxgb4: Cleanup register defines/MACROS

[Hariprasad Shenai]

Cleanup macros and register defines for consistency

Signed-off-by: Hariprasad Shenai <hariprasad-ut6Up61K2wZBDgjK7y7TUQ@public.gmane.org>
---
 drivers/infiniband/hw/cxgb4/cm.c          |    4 ++--
 drivers/infiniband/hw/cxgb4/t4fw_ri_api.h |    4 +++-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/infiniband/hw/cxgb4/cm.c b/drivers/infiniband/hw/cxgb4/cm.c
index 743b805..85167dc 100644
--- a/drivers/infiniband/hw/cxgb4/cm.c
+++ b/drivers/infiniband/hw/cxgb4/cm.c
@@ -675,7 +675,7 @@ static int send_connect(struct c4iw_ep *ep)
 	if (is_t5(ep->com.dev->rdev.lldi.adapter_type)) {
 		opt2 |= T5_OPT_2_VALID_F;
 		opt2 |= V_CONG_CNTRL(CONG_ALG_TAHOE);
-		opt2 |= CONG_CNTRL_VALID; /* OPT_2_ISS for T5 */
+		opt2 |= T5_ISS_F;
 	}
 	t4_set_arp_err_handler(skb, ep, act_open_req_arp_failure);
 
@@ -2217,7 +2217,7 @@ static void accept_cr(struct c4iw_ep *ep, struct sk_buff *skb,
 		u32 isn = (prandom_u32() & ~7UL) - 1;
 		opt2 |= T5_OPT_2_VALID_F;
 		opt2 |= V_CONG_CNTRL(CONG_ALG_TAHOE);
-		opt2 |= CONG_CNTRL_VALID; /* OPT_2_ISS for T5 */
+		opt2 |= T5_ISS_F;
 		rpl5 = (void *)rpl;
 		memset(&rpl5->iss, 0, roundup(sizeof(*rpl5)-sizeof(*rpl), 16));
 		if (peer2peer)
diff --git a/drivers/infiniband/hw/cxgb4/t4fw_ri_api.h b/drivers/infiniband/hw/cxgb4/t4fw_ri_api.h
index 5709e77..fe29e87 100644
--- a/drivers/infiniband/hw/cxgb4/t4fw_ri_api.h
+++ b/drivers/infiniband/hw/cxgb4/t4fw_ri_api.h
@@ -848,6 +848,8 @@ enum {                     /* TCP congestion control algorithms */
 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL)
 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL)
 
-#define CONG_CNTRL_VALID   (1 << 18)
+#define T5_ISS_S    18
+#define T5_ISS_V(x) ((x) << T5_ISS_S)
+#define T5_ISS_F    T5_ISS_V(1U)
 
 #endif /* _T4FW_RI_API_H_ */
-- 
1.7.1

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[PATCH for-next 2/4] iw_cxgb4: 32b platform fixes

[Hariprasad Shenai]

- get_dma_mr() was using ~0UL which is should be ~0ULL.  This causes the
DMA MR to get setup incorrectly in hardware.

- wr_log_show() needed a 64b divide function div64_u64() instead of doing
division directly.

- fixed warnings about recasting a pointer to a u64

Signed-off-by: Steve Wise <swise-7bPotxP6k4+P2YhJcF5u+vpXobYPEAuW@public.gmane.org>
Signed-off-by: Hariprasad Shenai <hariprasad-ut6Up61K2wZBDgjK7y7TUQ@public.gmane.org>
---
 drivers/infiniband/hw/cxgb4/cm.c     |    2 +-
 drivers/infiniband/hw/cxgb4/cq.c     |    6 +++---
 drivers/infiniband/hw/cxgb4/device.c |    6 +++---
 drivers/infiniband/hw/cxgb4/mem.c    |   10 +++++-----
 drivers/infiniband/hw/cxgb4/qp.c     |   14 +++++++-------
 5 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/infiniband/hw/cxgb4/cm.c b/drivers/infiniband/hw/cxgb4/cm.c
index 85167dc..7dbff7a 100644
--- a/drivers/infiniband/hw/cxgb4/cm.c
+++ b/drivers/infiniband/hw/cxgb4/cm.c
@@ -3578,7 +3578,7 @@ static void send_fw_pass_open_req(struct c4iw_dev *dev, struct sk_buff *skb,
 	 * TP will ignore any value > 0 for MSS index.
 	 */
 	req->tcb.opt0 = cpu_to_be64(MSS_IDX_V(0xF));
-	req->cookie = (unsigned long)skb;
+	req->cookie = (u64)(unsigned long)skb;
 
 	set_wr_txq(req_skb, CPL_PRIORITY_CONTROL, port_id);
 	ret = cxgb4_ofld_send(dev->rdev.lldi.ports[0], req_skb);
diff --git a/drivers/infiniband/hw/cxgb4/cq.c b/drivers/infiniband/hw/cxgb4/cq.c
index e9fd3a0..aed2b6b 100644
--- a/drivers/infiniband/hw/cxgb4/cq.c
+++ b/drivers/infiniband/hw/cxgb4/cq.c
@@ -55,7 +55,7 @@ static int destroy_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
 			V_FW_RI_RES_WR_NRES(1) |
 			FW_WR_COMPL_F);
 	res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
-	res_wr->cookie = (unsigned long) &wr_wait;
+	res_wr->cookie = (u64)(unsigned long)&wr_wait;
 	res = res_wr->res;
 	res->u.cq.restype = FW_RI_RES_TYPE_CQ;
 	res->u.cq.op = FW_RI_RES_OP_RESET;
@@ -125,7 +125,7 @@ static int create_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
 			V_FW_RI_RES_WR_NRES(1) |
 			FW_WR_COMPL_F);
 	res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
-	res_wr->cookie = (unsigned long) &wr_wait;
+	res_wr->cookie = (u64)(unsigned long)&wr_wait;
 	res = res_wr->res;
 	res->u.cq.restype = FW_RI_RES_TYPE_CQ;
 	res->u.cq.op = FW_RI_RES_OP_WRITE;
@@ -970,7 +970,7 @@ struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
 	}
 	PDBG("%s cqid 0x%0x chp %p size %u memsize %zu, dma_addr 0x%0llx\n",
 	     __func__, chp->cq.cqid, chp, chp->cq.size,
-	     chp->cq.memsize,
+	     (unsigned long)chp->cq.memsize,
 	     (unsigned long long) chp->cq.dma_addr);
 	return &chp->ibcq;
 err5:
diff --git a/drivers/infiniband/hw/cxgb4/device.c b/drivers/infiniband/hw/cxgb4/device.c
index 78ed883..3fbd53d 100644
--- a/drivers/infiniband/hw/cxgb4/device.c
+++ b/drivers/infiniband/hw/cxgb4/device.c
@@ -151,7 +151,7 @@ static int wr_log_show(struct seq_file *seq, void *v)
 	int prev_ts_set = 0;
 	int idx, end;
 
-#define ts2ns(ts) div64_ul((ts) * dev->rdev.lldi.cclk_ps, 1000)
+#define ts2ns(ts) div64_u64((ts) * dev->rdev.lldi.cclk_ps, 1000)
 
 	idx = atomic_read(&dev->rdev.wr_log_idx) &
 		(dev->rdev.wr_log_size - 1);
@@ -804,10 +804,10 @@ static int c4iw_rdev_open(struct c4iw_rdev *rdev)
 	     rdev->lldi.vr->qp.size,
 	     rdev->lldi.vr->cq.start,
 	     rdev->lldi.vr->cq.size);
-	PDBG("udb len 0x%x udb base %llx db_reg %p gts_reg %p qpshift %lu "
+	PDBG("udb len 0x%x udb base %p db_reg %p gts_reg %p qpshift %lu "
 	     "qpmask 0x%x cqshift %lu cqmask 0x%x\n",
 	     (unsigned)pci_resource_len(rdev->lldi.pdev, 2),
-	     (u64)pci_resource_start(rdev->lldi.pdev, 2),
+	     (void *)(unsigned long)pci_resource_start(rdev->lldi.pdev, 2),
 	     rdev->lldi.db_reg,
 	     rdev->lldi.gts_reg,
 	     rdev->qpshift, rdev->qpmask,
diff --git a/drivers/infiniband/hw/cxgb4/mem.c b/drivers/infiniband/hw/cxgb4/mem.c
index cb43c22..eca41a3 100644
--- a/drivers/infiniband/hw/cxgb4/mem.c
+++ b/drivers/infiniband/hw/cxgb4/mem.c
@@ -144,7 +144,7 @@ static int _c4iw_write_mem_inline(struct c4iw_rdev *rdev, u32 addr, u32 len,
 		if (i == (num_wqe-1)) {
 			req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR) |
 						    FW_WR_COMPL_F);
-			req->wr.wr_lo = (__force __be64)(unsigned long) &wr_wait;
+			req->wr.wr_lo = (__force __be64)(unsigned long)&wr_wait;
 		} else
 			req->wr.wr_hi = cpu_to_be32(FW_WR_OP_V(FW_ULPTX_WR));
 		req->wr.wr_mid = cpu_to_be32(
@@ -676,12 +676,12 @@ struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc)
 	mhp->attr.zbva = 0;
 	mhp->attr.va_fbo = 0;
 	mhp->attr.page_size = 0;
-	mhp->attr.len = ~0UL;
+	mhp->attr.len = ~0ULL;
 	mhp->attr.pbl_size = 0;
 
 	ret = write_tpt_entry(&rhp->rdev, 0, &stag, 1, php->pdid,
 			      FW_RI_STAG_NSMR, mhp->attr.perms,
-			      mhp->attr.mw_bind_enable, 0, 0, ~0UL, 0, 0, 0);
+			      mhp->attr.mw_bind_enable, 0, 0, ~0ULL, 0, 0, 0);
 	if (ret)
 		goto err1;
 
@@ -930,7 +930,7 @@ struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(struct ib_device *device,
 
 	PDBG("%s c4pl %p pll_len %u page_list %p dma_addr %pad\n",
 	     __func__, c4pl, c4pl->pll_len, c4pl->ibpl.page_list,
-	     &c4pl->dma_addr);
+	     (void *)(unsigned long)c4pl->dma_addr);
 
 	return &c4pl->ibpl;
 }
@@ -941,7 +941,7 @@ void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *ibpl)
 
 	PDBG("%s c4pl %p pll_len %u page_list %p dma_addr %pad\n",
 	     __func__, c4pl, c4pl->pll_len, c4pl->ibpl.page_list,
-	     &c4pl->dma_addr);
+	     (void *)(unsigned long)c4pl->dma_addr);
 
 	dma_free_coherent(&c4pl->dev->rdev.lldi.pdev->dev,
 			  c4pl->pll_len,
diff --git a/drivers/infiniband/hw/cxgb4/qp.c b/drivers/infiniband/hw/cxgb4/qp.c
index bb85d47..a0f12e1 100644
--- a/drivers/infiniband/hw/cxgb4/qp.c
+++ b/drivers/infiniband/hw/cxgb4/qp.c
@@ -275,7 +275,7 @@ static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
 			V_FW_RI_RES_WR_NRES(2) |
 			FW_WR_COMPL_F);
 	res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
-	res_wr->cookie = (unsigned long) &wr_wait;
+	res_wr->cookie = (u64)(unsigned long)&wr_wait;
 	res = res_wr->res;
 	res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
 	res->u.sqrq.op = FW_RI_RES_OP_WRITE;
@@ -1209,7 +1209,7 @@ static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
 	wqe->flowid_len16 = cpu_to_be32(
 		FW_WR_FLOWID_V(ep->hwtid) |
 		FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
-	wqe->cookie = (unsigned long) &ep->com.wr_wait;
+	wqe->cookie = (u64)(unsigned long)&ep->com.wr_wait;
 
 	wqe->u.fini.type = FW_RI_TYPE_FINI;
 	ret = c4iw_ofld_send(&rhp->rdev, skb);
@@ -1279,7 +1279,7 @@ static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
 		FW_WR_FLOWID_V(qhp->ep->hwtid) |
 		FW_WR_LEN16_V(DIV_ROUND_UP(sizeof(*wqe), 16)));
 
-	wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
+	wqe->cookie = (u64)(unsigned long)&qhp->ep->com.wr_wait;
 
 	wqe->u.init.type = FW_RI_TYPE_INIT;
 	wqe->u.init.mpareqbit_p2ptype =
@@ -1766,11 +1766,11 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
 		mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
 		insert_mmap(ucontext, mm2);
 		mm3->key = uresp.sq_db_gts_key;
-		mm3->addr = (__force unsigned long) qhp->wq.sq.udb;
+		mm3->addr = (u64)(unsigned long)qhp->wq.sq.udb;
 		mm3->len = PAGE_SIZE;
 		insert_mmap(ucontext, mm3);
 		mm4->key = uresp.rq_db_gts_key;
-		mm4->addr = (__force unsigned long) qhp->wq.rq.udb;
+		mm4->addr = (u64)(unsigned long)qhp->wq.rq.udb;
 		mm4->len = PAGE_SIZE;
 		insert_mmap(ucontext, mm4);
 		if (mm5) {
@@ -1786,9 +1786,9 @@ struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
 	INIT_LIST_HEAD(&qhp->db_fc_entry);
 	PDBG("%s sq id %u size %u memsize %zu num_entries %u "
 	     "rq id %u size %u memsize %zu num_entries %u\n", __func__,
-	     qhp->wq.sq.qid, qhp->wq.sq.size, qhp->wq.sq.memsize,
+	     qhp->wq.sq.qid, qhp->wq.sq.size, (unsigned long)qhp->wq.sq.memsize,
 	     attrs->cap.max_send_wr, qhp->wq.rq.qid, qhp->wq.rq.size,
-	     qhp->wq.rq.memsize, attrs->cap.max_recv_wr);
+	     (unsigned long)qhp->wq.rq.memsize, attrs->cap.max_recv_wr);
 	return &qhp->ibqp;
 err8:
 	kfree(mm5);
-- 
1.7.1

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[PATCH for-next 3/4] iw_cxgb4: use BAR2 GTS register for T5 kernel mode CQs

[Hariprasad Shenai]

For T5, we must not use the kdb/kgts registers, in order avoid db drops
under extreme loads.

Signed-off-by: Steve Wise <swise-7bPotxP6k4+P2YhJcF5u+vpXobYPEAuW@public.gmane.org>
Signed-off-by: Hariprasad Shenai <hariprasad-ut6Up61K2wZBDgjK7y7TUQ@public.gmane.org>
---
 drivers/infiniband/hw/cxgb4/cq.c |   15 +++++++++++----
 drivers/infiniband/hw/cxgb4/t4.h |    7 ++++---
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/infiniband/hw/cxgb4/cq.c b/drivers/infiniband/hw/cxgb4/cq.c
index aed2b6b..646caf9 100644
--- a/drivers/infiniband/hw/cxgb4/cq.c
+++ b/drivers/infiniband/hw/cxgb4/cq.c
@@ -156,12 +156,19 @@ static int create_cq(struct c4iw_rdev *rdev, struct t4_cq *cq,
 		goto err4;
 
 	cq->gen = 1;
-	cq->gts = rdev->lldi.gts_reg;
 	cq->rdev = rdev;
 	if (user) {
-		cq->ugts = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
-					(cq->cqid << rdev->cqshift);
-		cq->ugts &= PAGE_MASK;
+		u32 off = (cq->cqid << rdev->cqshift) & PAGE_MASK;
+
+		cq->ugts = (u64)rdev->bar2_pa + off;
+	} else if (is_t4(rdev->lldi.adapter_type)) {
+		cq->gts = rdev->lldi.gts_reg;
+		cq->qid_mask = -1U;
+	} else {
+		u32 off = ((cq->cqid << rdev->cqshift) & PAGE_MASK) + 12;
+
+		cq->gts = rdev->bar2_kva + off;
+		cq->qid_mask = rdev->qpmask;
 	}
 	return 0;
 err4:
diff --git a/drivers/infiniband/hw/cxgb4/t4.h b/drivers/infiniband/hw/cxgb4/t4.h
index c04e513..97f90e4 100644
--- a/drivers/infiniband/hw/cxgb4/t4.h
+++ b/drivers/infiniband/hw/cxgb4/t4.h
@@ -539,6 +539,7 @@ struct t4_cq {
 	size_t memsize;
 	__be64 bits_type_ts;
 	u32 cqid;
+	u32 qid_mask;
 	int vector;
 	u16 size; /* including status page */
 	u16 cidx;
@@ -563,12 +564,12 @@ static inline int t4_arm_cq(struct t4_cq *cq, int se)
 	set_bit(CQ_ARMED, &cq->flags);
 	while (cq->cidx_inc > CIDXINC_MASK) {
 		val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7) |
-		      INGRESSQID(cq->cqid);
+		      INGRESSQID(cq->cqid & cq->qid_mask);
 		writel(val, cq->gts);
 		cq->cidx_inc -= CIDXINC_MASK;
 	}
 	val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6) |
-	      INGRESSQID(cq->cqid);
+	      INGRESSQID(cq->cqid & cq->qid_mask);
 	writel(val, cq->gts);
 	cq->cidx_inc = 0;
 	return 0;
@@ -601,7 +602,7 @@ static inline void t4_hwcq_consume(struct t4_cq *cq)
 		u32 val;
 
 		val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7) |
-		      INGRESSQID(cq->cqid);
+		      INGRESSQID(cq->cqid & cq->qid_mask);
 		writel(val, cq->gts);
 		cq->cidx_inc = 0;
 	}
-- 
1.7.1

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[PATCH for-next 4/4] iw_cxgb4: enforce qp/cq id requirements

[Hariprasad Shenai]

Currently the iw_cxgb4 implementation requires the qp and cq qid densities
to match as well as the qp and cq id ranges.  So fail a device open if
the device configuration doesn't meet the requirements.

The reason for these restictions has to do with the fact that IQ qid X
has a UGTS register in the same bar2 page as EQ qid X.  Thus both qids
need to be allocated to the same user process for security reasons.
The logic that does this (the qpid allocator in iw_cxgb4/resource.c)
handles this but requires the above restrictions.

Signed-off-by: Steve Wise <swise-7bPotxP6k4+P2YhJcF5u+vpXobYPEAuW@public.gmane.org>
Signed-off-by: Hariprasad Shenai <hariprasad-ut6Up61K2wZBDgjK7y7TUQ@public.gmane.org>
---
 drivers/infiniband/hw/cxgb4/device.c |   23 +++++++++++++++++++++++
 1 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/drivers/infiniband/hw/cxgb4/device.c b/drivers/infiniband/hw/cxgb4/device.c
index 3fbd53d..ecb8ff2 100644
--- a/drivers/infiniband/hw/cxgb4/device.c
+++ b/drivers/infiniband/hw/cxgb4/device.c
@@ -785,6 +785,29 @@ static int c4iw_rdev_open(struct c4iw_rdev *rdev)
 	c4iw_init_dev_ucontext(rdev, &rdev->uctx);
 
 	/*
+	 * This implementation assumes udb_density == ucq_density!  Eventually
+	 * we might need to support this but for now fail the open. Also the
+	 * cqid and qpid range must match for now.
+	 */
+	if (rdev->lldi.udb_density != rdev->lldi.ucq_density) {
+		pr_err(MOD "%s: unsupported udb/ucq densities %u/%u\n",
+		       pci_name(rdev->lldi.pdev), rdev->lldi.udb_density,
+		       rdev->lldi.ucq_density);
+		err = -EINVAL;
+		goto err1;
+	}
+	if (rdev->lldi.vr->qp.start != rdev->lldi.vr->cq.start ||
+	    rdev->lldi.vr->qp.size != rdev->lldi.vr->cq.size) {
+		pr_err(MOD "%s: unsupported qp and cq id ranges "
+		       "qp start %u size %u cq start %u size %u\n",
+		       pci_name(rdev->lldi.pdev), rdev->lldi.vr->qp.start,
+		       rdev->lldi.vr->qp.size, rdev->lldi.vr->cq.size,
+		       rdev->lldi.vr->cq.size);
+		err = -EINVAL;
+		goto err1;
+	}
+
+	/*
 	 * qpshift is the number of bits to shift the qpid left in order
 	 * to get the correct address of the doorbell for that qp.
 	 */
-- 
1.7.1

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Re: [PATCH for-next 0/4] Misc. fixes and cleanup for iw_cxgb4

[Steve Wise]

Hey Doug/Roland,

Please include this in the 4.1 merge...

Thanks,

Steve.



On 3/19/2015 11:43 AM, Hariprasad Shenai wrote:
> Hi,
>
> This patch series changes a macro definition to be consistent with other
> register macro defines. Fixes for 32b platform, use BAR2 register for kernel
> mode CQ's and enforces qp/cq id requirements.
>
> The patches series is created against 'infiniband' tree for-next branch.
> And includes patches on iw_cxgb4 driver.
>
> We have included all the maintainers of respective drivers. Kindly review the
> change and let us know in case of any review comments.
>
> Thanks
>
> Hariprasad Shenai (4):
>    iw_cxgb4: Cleanup register defines/MACROS
>    iw_cxgb4: 32b platform fixes
>    iw_cxgb4: use BAR2 GTS register for T5 kernel mode CQs
>    iw_cxgb4: enforce qp/cq id requirements
>
>   drivers/infiniband/hw/cxgb4/cm.c          |    6 +++---
>   drivers/infiniband/hw/cxgb4/cq.c          |   21 ++++++++++++++-------
>   drivers/infiniband/hw/cxgb4/device.c      |   29 ++++++++++++++++++++++++++---
>   drivers/infiniband/hw/cxgb4/mem.c         |   10 +++++-----
>   drivers/infiniband/hw/cxgb4/qp.c          |   14 +++++++-------
>   drivers/infiniband/hw/cxgb4/t4.h          |    7 ++++---
>   drivers/infiniband/hw/cxgb4/t4fw_ri_api.h |    4 +++-
>   7 files changed, 62 insertions(+), 29 deletions(-)

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Re: [PATCH for-next 0/4] Misc. fixes and cleanup for iw_cxgb4

[Doug Ledford]

[-- Attachment #1: Type: text/plain, Size: 1673 bytes --]

On Wed, 2015-04-15 at 13:52 -0500, Steve Wise wrote:
> Hey Doug/Roland,
> 
> Please include this in the 4.1 merge...

These patches no longer apply cleanly.

> Thanks,
> 
> Steve.
> 
> 
> 
> On 3/19/2015 11:43 AM, Hariprasad Shenai wrote:
> > Hi,
> >
> > This patch series changes a macro definition to be consistent with other
> > register macro defines. Fixes for 32b platform, use BAR2 register for kernel
> > mode CQ's and enforces qp/cq id requirements.
> >
> > The patches series is created against 'infiniband' tree for-next branch.
> > And includes patches on iw_cxgb4 driver.
> >
> > We have included all the maintainers of respective drivers. Kindly review the
> > change and let us know in case of any review comments.
> >
> > Thanks
> >
> > Hariprasad Shenai (4):
> >    iw_cxgb4: Cleanup register defines/MACROS
> >    iw_cxgb4: 32b platform fixes
> >    iw_cxgb4: use BAR2 GTS register for T5 kernel mode CQs
> >    iw_cxgb4: enforce qp/cq id requirements
> >
> >   drivers/infiniband/hw/cxgb4/cm.c          |    6 +++---
> >   drivers/infiniband/hw/cxgb4/cq.c          |   21 ++++++++++++++-------
> >   drivers/infiniband/hw/cxgb4/device.c      |   29 ++++++++++++++++++++++++++---
> >   drivers/infiniband/hw/cxgb4/mem.c         |   10 +++++-----
> >   drivers/infiniband/hw/cxgb4/qp.c          |   14 +++++++-------
> >   drivers/infiniband/hw/cxgb4/t4.h          |    7 ++++---
> >   drivers/infiniband/hw/cxgb4/t4fw_ri_api.h |    4 +++-
> >   7 files changed, 62 insertions(+), 29 deletions(-)
> 


-- 
Doug Ledford <dledford-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
              GPG KeyID: 0E572FDD



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RE: [PATCH for-next 0/4] Misc. fixes and cleanup for iw_cxgb4

[Steve Wise]

Ok, Hari can you please resubmit.   Should it be based on your github for-4.1 branch? 





> -----Original Message-----
> From: Doug Ledford [mailto:dledford-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org]
> Sent: Wednesday, April 15, 2015 3:33 PM
> To: Steve Wise
> Cc: roland-BHEL68pLQRGGvPXPguhicg@public.gmane.org; Hariprasad Shenai; linux-rdma-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; nirranjan-ut6Up61K2wZBDgjK7y7TUQ@public.gmane.org; kumaras-ut6Up61K2wZBDgjK7y7TUQ@public.gmane.org
> Subject: Re: [PATCH for-next 0/4] Misc. fixes and cleanup for iw_cxgb4
> 
> On Wed, 2015-04-15 at 13:52 -0500, Steve Wise wrote:
> > Hey Doug/Roland,
> >
> > Please include this in the 4.1 merge...
> 
> These patches no longer apply cleanly.
> 
> > Thanks,
> >
> > Steve.
> >
> >
> >
> > On 3/19/2015 11:43 AM, Hariprasad Shenai wrote:
> > > Hi,
> > >
> > > This patch series changes a macro definition to be consistent with other
> > > register macro defines. Fixes for 32b platform, use BAR2 register for kernel
> > > mode CQ's and enforces qp/cq id requirements.
> > >
> > > The patches series is created against 'infiniband' tree for-next branch.
> > > And includes patches on iw_cxgb4 driver.
> > >
> > > We have included all the maintainers of respective drivers. Kindly review the
> > > change and let us know in case of any review comments.
> > >
> > > Thanks
> > >
> > > Hariprasad Shenai (4):
> > >    iw_cxgb4: Cleanup register defines/MACROS
> > >    iw_cxgb4: 32b platform fixes
> > >    iw_cxgb4: use BAR2 GTS register for T5 kernel mode CQs
> > >    iw_cxgb4: enforce qp/cq id requirements
> > >
> > >   drivers/infiniband/hw/cxgb4/cm.c          |    6 +++---
> > >   drivers/infiniband/hw/cxgb4/cq.c          |   21 ++++++++++++++-------
> > >   drivers/infiniband/hw/cxgb4/device.c      |   29 ++++++++++++++++++++++++++---
> > >   drivers/infiniband/hw/cxgb4/mem.c         |   10 +++++-----
> > >   drivers/infiniband/hw/cxgb4/qp.c          |   14 +++++++-------
> > >   drivers/infiniband/hw/cxgb4/t4.h          |    7 ++++---
> > >   drivers/infiniband/hw/cxgb4/t4fw_ri_api.h |    4 +++-
> > >   7 files changed, 62 insertions(+), 29 deletions(-)
> >
> 
> 
> --
> Doug Ledford <dledford-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>               GPG KeyID: 0E572FDD
> 


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Re: [PATCH for-next 0/4] Misc. fixes and cleanup for iw_cxgb4

[Doug Ledford]

[-- Attachment #1: Type: text/plain, Size: 2648 bytes --]

On Wed, 2015-04-15 at 15:55 -0500, Steve Wise wrote:
> Ok, Hari can you please resubmit.   Should it be based on your github for-4.1 branch? 

Yes please.

> 
> 
> 
> 
> > -----Original Message-----
> > From: Doug Ledford [mailto:dledford-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org]
> > Sent: Wednesday, April 15, 2015 3:33 PM
> > To: Steve Wise
> > Cc: roland-BHEL68pLQRGGvPXPguhicg@public.gmane.org; Hariprasad Shenai; linux-rdma-u79uwXL29TbrhsbdSgBK9A@public.gmane.orgrg; nirranjan-ut6Up61K2wZBDgjK7y7TUQ@public.gmane.org; kumaras-ut6Up61K2wZBDgjK7y7TUQ@public.gmane.org
> > Subject: Re: [PATCH for-next 0/4] Misc. fixes and cleanup for iw_cxgb4
> > 
> > On Wed, 2015-04-15 at 13:52 -0500, Steve Wise wrote:
> > > Hey Doug/Roland,
> > >
> > > Please include this in the 4.1 merge...
> > 
> > These patches no longer apply cleanly.
> > 
> > > Thanks,
> > >
> > > Steve.
> > >
> > >
> > >
> > > On 3/19/2015 11:43 AM, Hariprasad Shenai wrote:
> > > > Hi,
> > > >
> > > > This patch series changes a macro definition to be consistent with other
> > > > register macro defines. Fixes for 32b platform, use BAR2 register for kernel
> > > > mode CQ's and enforces qp/cq id requirements.
> > > >
> > > > The patches series is created against 'infiniband' tree for-next branch.
> > > > And includes patches on iw_cxgb4 driver.
> > > >
> > > > We have included all the maintainers of respective drivers. Kindly review the
> > > > change and let us know in case of any review comments.
> > > >
> > > > Thanks
> > > >
> > > > Hariprasad Shenai (4):
> > > >    iw_cxgb4: Cleanup register defines/MACROS
> > > >    iw_cxgb4: 32b platform fixes
> > > >    iw_cxgb4: use BAR2 GTS register for T5 kernel mode CQs
> > > >    iw_cxgb4: enforce qp/cq id requirements
> > > >
> > > >   drivers/infiniband/hw/cxgb4/cm.c          |    6 +++---
> > > >   drivers/infiniband/hw/cxgb4/cq.c          |   21 ++++++++++++++-------
> > > >   drivers/infiniband/hw/cxgb4/device.c      |   29 ++++++++++++++++++++++++++---
> > > >   drivers/infiniband/hw/cxgb4/mem.c         |   10 +++++-----
> > > >   drivers/infiniband/hw/cxgb4/qp.c          |   14 +++++++-------
> > > >   drivers/infiniband/hw/cxgb4/t4.h          |    7 ++++---
> > > >   drivers/infiniband/hw/cxgb4/t4fw_ri_api.h |    4 +++-
> > > >   7 files changed, 62 insertions(+), 29 deletions(-)
> > >
> > 
> > 
> > --
> > Doug Ledford <dledford-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> >               GPG KeyID: 0E572FDD
> > 
> 
> 


-- 
Doug Ledford <dledford-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
              GPG KeyID: 0E572FDD



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