From mboxrd@z Thu Jan  1 00:00:00 1970
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Subject: Re: RFC on writel and writel_relaxed
Date: Fri, 23 Mar 2018 11:16:08 +1100
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To: Sinan Kaya <okaya@codeaurora.org>, Oliver <oohall@gmail.com>
Cc: "linux-rdma@vger.kernel.org" <linux-rdma@vger.kernel.org>, Marc Zyngier <marc.zyngier@arm.com>, linuxppc dev list <linuxppc-dev@lists.ozlabs.org>, Will Deacon <will.deacon@arm.com>
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On Thu, 2018-03-22 at 12:51 -0500, Sinan Kaya wrote:
> On 3/22/2018 8:52 AM, Benjamin Herrenschmidt wrote:
> > > > No, it's not sufficient.
> > 
> > Just to clarify ... barrier() is just a compiler barrier, it means the
> > compiler will generate things in the order they are written. This isn't
> > sufficient on archs with an OO memory model, where an actual memory
> > barrier instruction needs to be emited.
> 
> Surprisingly, ARM64 GCC compiler generates a write barrier as
> opposed to preventing code reordering.
> 
> I was curious if this is an ARM only thing or not. 

Are you sure of that ? I thought it's the ARM implementation of writel
that had an explicit write barrier in it:

#define writel(v,c)		({ __iowmb(); writel_relaxed((v),(c)); })

And __iowmb() is 

#define __iowmb()		wmb()

Note, I'm a bit dubious about this in ARM:

#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(); __v; }

Will, Marc, on powerpc, we put a sync *before* the read in readl etc...

The reasoning was there could be some DMA setup followed by a side
effect readl rather than a side effect writel to trigger a DMA. Granted
I wouldn't expect modern devices to be that stupid, but I have vague
memory of some devices back in the day having that sort of read ops.

In general, I though the model offerred by x86 and thus by Linux
readl/writel was full synchronization both before and after the MMIO,
vs either other MMIO or all other forms of ops (cachable memory, locks
etc...).

Also, can't the above readl_relaxed leak out of a lock ?

Cheers,
Ben.