From: Weihang Li <liweihang@huawei.com>
To: <dledford@redhat.com>, <jgg@ziepe.ca>
Cc: <leon@kernel.org>, <linux-rdma@vger.kernel.org>, <linuxarm@huawei.com>
Subject: [PATCH v3 for-next 0/2] RDMA/hns: Add supports for stash
Date: Fri, 20 Nov 2020 18:17:18 +0800 [thread overview]
Message-ID: <1605867440-2413-1-git-send-email-liweihang@huawei.com> (raw)
Stash is a mechanism that uses the core information carried by the ARM AXI
bus to access the L3 cache. The CPU and I/O subsystems can access the L3
cache consistently by enabling stash, so the performance can be improved.
Changes since v2:
- Replace hr_reg_set() with hr_reg_enable(), which supports to set a single
bit.
link: https://patchwork.kernel.org/project/linux-rdma/cover/1605527919-48769-1-git-send-email-liweihang@huawei.com/
Changes since v1:
- Fix comments from Jason about the unused macros.
- Rewrite hr_reg_set() to make it easier for driver to define and set a
field.
link: https://patchwork.kernel.org/project/linux-rdma/cover/1601458452-55263-1-git-send-email-liweihang@huawei.com/
Lang Cheng (2):
RDMA/hns: Add support for CQ stash
RDMA/hns: Add support for QP stash
drivers/infiniband/hw/hns/hns_roce_common.h | 10 +++++++
drivers/infiniband/hw/hns/hns_roce_device.h | 1 +
drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 9 +++++++
drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 41 ++++++++++++++++++-----------
4 files changed, 45 insertions(+), 16 deletions(-)
--
2.8.1
next reply other threads:[~2020-11-20 10:19 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-20 10:17 Weihang Li [this message]
2020-11-20 10:17 ` [PATCH v3 for-next 1/2] RDMA/hns: Add support for CQ stash Weihang Li
2020-11-20 20:13 ` Jason Gunthorpe
2020-11-26 6:56 ` liweihang
2020-11-20 10:17 ` [PATCH v3 for-next 2/2] RDMA/hns: Add support for QP stash Weihang Li
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