From: Weihang Li <liweihang@huawei.com>
To: <dledford@redhat.com>, <jgg@ziepe.ca>
Cc: <leon@kernel.org>, <linux-rdma@vger.kernel.org>, <linuxarm@huawei.com>
Subject: [PATCH for-next 03/11] RDMA/hns: Do shift on traffic class of UD SQ WQE
Date: Wed, 2 Dec 2020 16:59:05 +0800 [thread overview]
Message-ID: <1606899553-54592-4-git-send-email-liweihang@huawei.com> (raw)
In-Reply-To: <1606899553-54592-1-git-send-email-liweihang@huawei.com>
The high 6 bits of traffic class in GRH is DSCP (Differentiated Services
Codepoint), the driver should shift it before the hardware gets it. In
addition, there is no need to check whether it's RoCEv2 when filling TC
into QPC because the DSCP field is meaningless for RoCEv1.
Fixes: 606bf89e98ef ("RDMA/hns: Refactor for hns_roce_v2_modify_qp function")
Fixes: d6a3627e311c ("RDMA/hns: Optimize wqe buffer set flow for post send")
Signed-off-by: Weihang Li <liweihang@huawei.com>
---
drivers/infiniband/hw/hns/hns_roce_device.h | 2 ++
drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 13 +++++--------
2 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h
index a5c6bb0..1981501 100644
--- a/drivers/infiniband/hw/hns/hns_roce_device.h
+++ b/drivers/infiniband/hw/hns/hns_roce_device.h
@@ -119,6 +119,8 @@
#define HNS_ROCE_QP_BANK_NUM 8
+#define DSCP_SHIFT 2
+
/* The chip implementation of the consumer index is calculated
* according to twice the actual EQ depth
*/
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index 8d37067..13c8a2c 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -430,7 +430,8 @@ static int fill_ud_av(struct hns_roce_v2_ud_send_wqe *ud_sq_wqe,
roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_M,
V2_UD_SEND_WQE_BYTE_36_HOPLIMIT_S, ah->av.hop_limit);
roce_set_field(ud_sq_wqe->byte_36, V2_UD_SEND_WQE_BYTE_36_TCLASS_M,
- V2_UD_SEND_WQE_BYTE_36_TCLASS_S, ah->av.tclass);
+ V2_UD_SEND_WQE_BYTE_36_TCLASS_S,
+ ah->av.tclass >> DSCP_SHIFT);
roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_M,
V2_UD_SEND_WQE_BYTE_40_FLOW_LABEL_S, ah->av.flowlabel);
roce_set_field(ud_sq_wqe->byte_40, V2_UD_SEND_WQE_BYTE_40_SL_M,
@@ -4596,15 +4597,11 @@ static int hns_roce_v2_set_path(struct ib_qp *ibqp,
roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_HOP_LIMIT_M,
V2_QPC_BYTE_24_HOP_LIMIT_S, 0);
- if (is_udp)
- roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
- V2_QPC_BYTE_24_TC_S, grh->traffic_class >> 2);
- else
- roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
- V2_QPC_BYTE_24_TC_S, grh->traffic_class);
-
+ roce_set_field(context->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
+ V2_QPC_BYTE_24_TC_S, grh->traffic_class >> DSCP_SHIFT);
roce_set_field(qpc_mask->byte_24_mtu_tc, V2_QPC_BYTE_24_TC_M,
V2_QPC_BYTE_24_TC_S, 0);
+
roce_set_field(context->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
V2_QPC_BYTE_28_FL_S, grh->flow_label);
roce_set_field(qpc_mask->byte_28_at_fl, V2_QPC_BYTE_28_FL_M,
--
2.8.1
next prev parent reply other threads:[~2020-12-02 9:02 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-02 8:59 [PATCH for-next 00/11] RDMA/hns: Updates for 5.11 Weihang Li
2020-12-02 8:59 ` [PATCH for-next 01/11] RDMA/hns: Limit the length of data copied between kernel and userspace Weihang Li
2020-12-02 8:59 ` [PATCH for-next 02/11] RDMA/hns: Normalization the judgment of some features Weihang Li
2020-12-02 8:59 ` Weihang Li [this message]
2020-12-04 10:03 ` [PATCH for-next 03/11] RDMA/hns: Do shift on traffic class of UD SQ WQE Lang Cheng
2020-12-04 10:10 ` liweihang
2020-12-02 8:59 ` [PATCH for-next 04/11] RDMA/hns: Avoid filling sl in high 3 bits of vlan_id Weihang Li
2020-12-02 8:59 ` [PATCH for-next 05/11] RDMA/hns: WARN_ON if get a reserved sl from users Weihang Li
2020-12-02 8:59 ` [PATCH for-next 06/11] RDMA/hns: Remove unnecessary access right set during INIT2INIT Weihang Li
2020-12-02 8:59 ` [PATCH for-next 07/11] RDMA/hns: Fix coding style issues Weihang Li
2020-12-02 8:59 ` [PATCH for-next 08/11] RDMA/hns: Clear redundant variable initialization Weihang Li
2020-12-02 8:59 ` [PATCH for-next 09/11] RDMA/hns: Fix incorrect symbol types Weihang Li
2020-12-02 8:59 ` [PATCH for-next 10/11] RDMA/hns: Fix inaccurate prints Weihang Li
2020-12-02 8:59 ` [PATCH for-next 11/11] RDMA/hns: Simplify AEQE process for different types of queue Weihang Li
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