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Wed, 22 Oct 2025 23:44:54 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , "Carolina Jubran" , Dragos Tatulea Subject: [PATCH net-next 2/7] net/mlx5e: Use TIR API in mlx5e_modify_tirs_lb() Date: Thu, 23 Oct 2025 09:43:35 +0300 Message-ID: <1761201820-923638-3-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 In-Reply-To: <1761201820-923638-1-git-send-email-tariqt@nvidia.com> References: <1761201820-923638-1-git-send-email-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A34C:EE_|CYYPR12MB8701:EE_ X-MS-Office365-Filtering-Correlation-Id: fce1a999-465b-4df3-6865-08de11ffb688 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?4znl1lKlsu7PA7yeRNhrF5f3ZN6bfYW3XWU9lXbqYr63xRE0whQVYXuJCkDu?= =?us-ascii?Q?8c2wmKBGYQKn5mS+EaHuo7Apyfl9/zJdTGlR48ySEpogzAqXLhFoOFBL6KWI?= =?us-ascii?Q?TdiMtl614XH/zxKDWk2ig9v+iGyAg8th3avEstKq4ggoRZOGQhaEbiQ2F5U2?= =?us-ascii?Q?nrNauVH0Di0MIaq4WICUZzg89xGBOF1o3Ql9AQbcGNkghaSsF63+8b/CgKWK?= =?us-ascii?Q?4w0c78RzmN6107n2ihMYgY5kmpnzHYrZQ7j5jvF/+084tfaSgnOvyhROLDMp?= =?us-ascii?Q?oLY4/vr6u1mSB6JDFfIRtJYNfo215SjYR+YpBJL058cvB3eC33txapQz3abY?= =?us-ascii?Q?rCRj5xUBThX+VMlGq866HDl3+RfbGmu09NFv1Sif3RcHGO4GQr7QBbRo9beN?= =?us-ascii?Q?H5Nhpw/2MH4+y8DuEoGE+fwQtEAgMHttW/hIWWSGuE210Nd0LEuUMmcgFIg5?= =?us-ascii?Q?xLiZJ4AeBqmbxTKhE/Lk/RTnOv/bG3SFcPhiSDb0f1NjVxwQw7Tl1wEGsqg7?= =?us-ascii?Q?e6w4NF7GXI5KNzxhqflAmkg3sdB5WEiompTrIAA/8R97EawGRswRTDpN1v7w?= =?us-ascii?Q?xVDDJHV6OTsVAKPrif9SjLOB6ljhmwxZ4kbT6JQRD4qQCjktfa/rQWsnqFma?= =?us-ascii?Q?H6DjaBomOq78SOeKEiTKrCQ5Gx8O4+j+57SCDZmtCpAEr+73HyawVQCISHw4?= =?us-ascii?Q?Vnv0enYAhR/bofkFuMmSIyPGAMpQbNlYNyyFwPCAGsUV+mSgBIs1MJ3FhjzH?= =?us-ascii?Q?v/Hs2Ll/M7lRB6nHdfD3i0f8EuYjh2WOkY6opAb5SR4N1WtnJN0dQPwwwak0?= =?us-ascii?Q?zR3dP9o1Zvd2Hnsw35K+subMSXOt/Ck0SfYsDYHSHb6vhbrjfTsP1hkCNLr5?= =?us-ascii?Q?bqE+ZEmJ6TJOrdtcVV8Eqz6Htb2FOsUlG/I2rpAwuuvDQSy67dS3QbctlCTo?= =?us-ascii?Q?hVVr+c93H8TxJPa2U/5tdie5Mo/YrmH1ugZn4asbZn3k218m/McJraihMtlD?= =?us-ascii?Q?WdoHKN6OeHMQzr7QJVM0gh7+tZMZ5komYmTq+FXEOzz5kNRpELWcKB2E8xXD?= =?us-ascii?Q?wBEeiUhQ7A7YxDyfqoz+k5En5+ZufQOctDmx6NSbLy1pDIHifhCXzxecmzcq?= =?us-ascii?Q?7txZu7FmUnydRj7cBgsF1KCKjCDKRdcson4CWkSD6FqI6YcB9R1WQZ5c1r5n?= =?us-ascii?Q?EyAxMP0uBsELuOWiDW0wsSjD14KFyGh670VDBWsi1trIzTGBPMspyvr02sh1?= =?us-ascii?Q?QfgjfvnEU78Ukl6/2Y3PmUcC2BUriV/DXnykVZBl9xYCbuqp2klDs2EKwlCF?= =?us-ascii?Q?9fW1VcEe3a1OIpFJhO9Hd1qcXOVxk/w7a21zYZ4G3nU6GOT/1/j4gTv/+CO7?= =?us-ascii?Q?HYlKpUUxk5s8xFoC1t4VsNOH9bCXmN8eWMun3jhjwhxTVVebjEseFpDybuYp?= =?us-ascii?Q?uAZdTLXDhJgLEgRM0EA9jEJCXEHgqE2YCuVUcbb50nek0Ef85yoZ8PCqRdbL?= =?us-ascii?Q?qeqJqige/jLslB9CScxXMXcSODA8x4QtNA0TGFHqlo5Pa1wSU8EiXEZsncI0?= =?us-ascii?Q?w1jt64Xw0Rgga6BiBus=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2025 06:45:10.8418 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fce1a999-465b-4df3-6865-08de11ffb688 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8701 Extend the TIR API and use it in mlx5e_modify_tirs_lb() instead of the explicit modify_tir code. Signed-off-by: Tariq Toukan Reviewed-by: Carolina Jubran Reviewed-by: Dragos Tatulea --- .../net/ethernet/mellanox/mlx5/core/en/tir.c | 29 +++++++++++++++++-- .../net/ethernet/mellanox/mlx5/core/en/tir.h | 3 ++ .../ethernet/mellanox/mlx5/core/en_common.c | 29 +++++-------------- 3 files changed, 37 insertions(+), 24 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tir.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tir.c index 19499072f67f..0b55e77f19c8 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tir.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tir.c @@ -146,6 +146,31 @@ void mlx5e_tir_builder_build_direct(struct mlx5e_tir_builder *builder) MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8); } +static void mlx5e_tir_context_self_lb_block(void *tirc, bool enable_uc_lb, + bool enable_mc_lb) +{ + u8 lb_flags = 0; + + if (enable_uc_lb) + lb_flags = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; + if (enable_mc_lb) + lb_flags |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; + + MLX5_SET(tirc, tirc, self_lb_block, lb_flags); +} + +void mlx5e_tir_builder_build_self_lb_block(struct mlx5e_tir_builder *builder, + bool enable_uc_lb, + bool enable_mc_lb) +{ + void *tirc = mlx5e_tir_builder_get_tirc(builder); + + if (builder->modify) + MLX5_SET(modify_tir_in, builder->in, bitmask.self_lb_en, 1); + + mlx5e_tir_context_self_lb_block(tirc, enable_uc_lb, enable_mc_lb); +} + void mlx5e_tir_builder_build_tls(struct mlx5e_tir_builder *builder) { void *tirc = mlx5e_tir_builder_get_tirc(builder); @@ -153,9 +178,7 @@ void mlx5e_tir_builder_build_tls(struct mlx5e_tir_builder *builder) WARN_ON(builder->modify); MLX5_SET(tirc, tirc, tls_en, 1); - MLX5_SET(tirc, tirc, self_lb_block, - MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST | - MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST); + mlx5e_tir_context_self_lb_block(tirc, true, true); } int mlx5e_tir_init(struct mlx5e_tir *tir, struct mlx5e_tir_builder *builder, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tir.h b/drivers/net/ethernet/mellanox/mlx5/core/en/tir.h index e8df3aaf6562..958eeb959a19 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/tir.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tir.h @@ -35,6 +35,9 @@ void mlx5e_tir_builder_build_rss(struct mlx5e_tir_builder *builder, const struct mlx5e_rss_params_traffic_type *rss_tt, bool inner); void mlx5e_tir_builder_build_direct(struct mlx5e_tir_builder *builder); +void mlx5e_tir_builder_build_self_lb_block(struct mlx5e_tir_builder *builder, + bool enable_uc_lb, + bool enable_mc_lb); void mlx5e_tir_builder_build_tls(struct mlx5e_tir_builder *builder); struct mlx5_core_dev; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c index 376a018b2db1..fad6b761f622 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c @@ -250,43 +250,30 @@ void mlx5e_destroy_mdev_resources(struct mlx5_core_dev *mdev) int mlx5e_modify_tirs_lb(struct mlx5_core_dev *mdev, bool enable_uc_lb, bool enable_mc_lb) { + struct mlx5e_tir_builder *builder; struct mlx5e_tir *tir; - u8 lb_flags = 0; int err = 0; - u32 tirn = 0; - int inlen; - void *in; - inlen = MLX5_ST_SZ_BYTES(modify_tir_in); - in = kvzalloc(inlen, GFP_KERNEL); - if (!in) + builder = mlx5e_tir_builder_alloc(true); + if (!builder) return -ENOMEM; - if (enable_uc_lb) - lb_flags = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST; - - if (enable_mc_lb) - lb_flags |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST; - - if (lb_flags) - MLX5_SET(modify_tir_in, in, ctx.self_lb_block, lb_flags); - - MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1); + mlx5e_tir_builder_build_self_lb_block(builder, enable_uc_lb, + enable_mc_lb); mutex_lock(&mdev->mlx5e_res.hw_objs.td.list_lock); list_for_each_entry(tir, &mdev->mlx5e_res.hw_objs.td.tirs_list, list) { - tirn = tir->tirn; - err = mlx5_core_modify_tir(mdev, tirn, in); + err = mlx5e_tir_modify(tir, builder); if (err) break; } mutex_unlock(&mdev->mlx5e_res.hw_objs.td.list_lock); - kvfree(in); + mlx5e_tir_builder_free(builder); if (err) mlx5_core_err(mdev, "modify tir(0x%x) enable_lb uc(%d) mc(%d) failed, %d\n", - tirn, + mlx5e_tir_get_tirn(tir), enable_uc_lb, enable_mc_lb, err); return err; -- 2.31.1