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From: Jason Gunthorpe <jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
To: Steve Wise <swise-7bPotxP6k4+P2YhJcF5u+vpXobYPEAuW@public.gmane.org>
Cc: dledford-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org,
	linux-rdma-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH RFC] libibverbs: add ARM64 memory barrier macros
Date: Thu, 19 May 2016 12:05:52 -0600	[thread overview]
Message-ID: <20160519180552.GA26130@obsidianresearch.com> (raw)
In-Reply-To: <060701d1b1e7$dc7e1ff0$957a5fd0$@opengridcomputing.com>

On Thu, May 19, 2016 at 11:02:36AM -0500, Steve Wise wrote:

> Looking at the documentation, it is not clear to me which parameter value passed
> to atomic_thread_fence() maps to each of the mb services.  Is it correct to
> think that if I get it right, the resulting assembly should be what we currently
> have for the mb services?

You can review

https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html

Hurm.

So, I'd say libibverbs is kinda broken here, as it is using a model
that is different from the kernel model. Sigh, it actually looks like
kinda a mess because provider libraries are abusing the primitives for
lots of different things. :(

This is the mapping that matches the definitions of the barriers:

 wmb can be memory_order_release
 rmb can be memory_order_acquire
 mb can be memory_order_seq_cst

On x86 this is similar as what we have today, but slightly less
explicit than the kernel model. Seems OK

On ARMv8 this would be DMB slightly weaker than the
kernel's DSB (My read suggests this is OK for PCI vs system memory
on coherent ARM?)

PPC will be lwsync not sync (not OK)

ia64 will both use mf for mb, but different otherwise (not OK)

No idea about the others.

C11 atomics are only specified for system memory to system memory,
they are undefined when working with device MMIO memory - this is why
some of the above are 'not OK'.

You could provide the above as the new default, maybe even use it on
some of the archs, like armv8/x86 if you think the dmb is OK.

An even better suggestion is to try and clean up some of this mess by
being more explicit:

 /* Guarentee all system memory writes are visible by the device
    before value's write is seen at the device */
 mmio_barrier_write32(void *ptr, uint32_t value);

Most everything else can then safely use C11 atomics as it is not
working with device memory.

But that is too hard with all our providers sprinkled around in so
many git trees :(

Jason
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  parent reply	other threads:[~2016-05-19 18:05 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-18 21:16 [PATCH RFC] libibverbs: add ARM64 memory barrier macros Steve Wise
     [not found] ` <20160518220302.81260E09E9-/5N3P9jjx0xzbRFIqnYvSA@public.gmane.org>
2016-05-18 22:28   ` Jason Gunthorpe
     [not found]     ` <20160518222857.GB23835-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2016-05-19 16:02       ` Steve Wise
2016-05-19 16:35         ` Steve Wise
2016-05-19 18:05         ` Jason Gunthorpe [this message]
     [not found]           ` <20160519180552.GA26130-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2016-05-19 18:54             ` Steve Wise
2016-05-19 19:28               ` Jason Gunthorpe
     [not found]                 ` <20160519192805.GA32668-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2016-05-20  9:44                   ` Gabriele Svelto
     [not found]                     ` <b4eb5c63-9f20-b927-ebc8-f8016accc93c-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-05-24 17:22                       ` Jason Gunthorpe
2016-05-19 20:14             ` Bart Van Assche
     [not found]               ` <573E1EC3.5000907-XdAiOPVOjttBDgjK7y7TUQ@public.gmane.org>
2016-05-19 20:57                 ` Jason Gunthorpe

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