Re: [PATCH RFC] libibverbs: add ARM64 memory barrier macros

[Jason Gunthorpe <jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>]

On Thu, May 19, 2016 at 01:14:59PM -0700, Bart Van Assche wrote:
> On 05/19/2016 11:05 AM, Jason Gunthorpe wrote:
> >This is the mapping that matches the definitions of the barriers:
> >
> >  wmb can be memory_order_release
> >  rmb can be memory_order_acquire
> >  mb can be memory_order_seq_cst
> 
> This is not correct. Acquire and release, at least as defined by
> Gharachorloo in 1991, have another meaning than the mentioned barrier
> instructions. Acquire and release are labels that can be applied to load and
> store instructions respectively.

C11 uses a common language for the coherency requirement in multiple
contexts
- Load/store
- fence (ie a barrier)
- exchanges
- bit set/test

In a load/store context the ordering is associated with a single
memory op, like your paper describes. In the fence context there is no
memory op, the ordering acts on all memory ops..

Jason
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