From: Jason Gunthorpe <jgunthorpe-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
To: Stephen Warren <swarren-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cc: Yishai Hadas <yishaih-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>,
linux-rdma-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: ConnectX-3 on non-coherent AARCH64 system
Date: Fri, 10 Mar 2017 10:06:26 -0700 [thread overview]
Message-ID: <20170310170626.GE22960@obsidianresearch.com> (raw)
In-Reply-To: <b01684b6-ba4a-65cc-ea20-b578e1e2fa2e-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On Thu, Mar 09, 2017 at 04:59:40PM -0700, Stephen Warren wrote:
> However, when I run the same test on a (non-cache-coherent) AArch64 (ARMv8)
> machine (Cortex-A57, NVIDIA Tegra), the application does not work. In
> particular, ivc_poll_cq() returns -2 when the application waits for an
> ibv_post_send/recv() to complete.
User space verbs are not supported on non-cache-coherent architectures
for kernel bypass adapters and probably never will be.
Ideally the kernel would not create the uverbs device for DMA drivers
on such architectures.. Is there a kernel API to detect cache
incoherence?
> than e.g. the kernel filling in the CQ), and there don't appear to be any
> cache invalidation operations anywhere in libmlx4 (I'm not even sure if
> cache manipulation is possible from user-space on ARM). I also
> couldn't find
Precisely.
Jason
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next prev parent reply other threads:[~2017-03-10 17:06 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-09 23:59 ConnectX-3 on non-coherent AARCH64 system Stephen Warren
[not found] ` <b01684b6-ba4a-65cc-ea20-b578e1e2fa2e-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-03-10 17:06 ` Jason Gunthorpe [this message]
[not found] ` <20170310170626.GE22960-ePGOBjL8dl3ta4EC/59zMFaTQe2KTcn/@public.gmane.org>
2017-03-13 16:43 ` Stephen Warren
[not found] ` <40698e27-8b17-df09-8165-40420f16a37e-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2017-03-13 16:55 ` Jason Gunthorpe
2017-03-13 17:38 ` Christoph Lameter
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