From: Leon Romanovsky <leon-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Shiraz Saleem <shiraz.saleem-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Cc: dledford-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org,
linux-rdma-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
e1000-rdma-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org,
Mustafa Ismail
<mustafa.ismail-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Subject: Re: [PATCH 2/5] i40iw: Do not generate CQE for RTR on QP flush
Date: Sun, 1 Oct 2017 09:19:28 +0300 [thread overview]
Message-ID: <20171001061928.GD2031@mtr-leonro.local> (raw)
In-Reply-To: <20170930012942.9128-3-shiraz.saleem-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
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On Fri, Sep 29, 2017 at 08:29:39PM -0500, Shiraz Saleem wrote:
> From: Mustafa Ismail <mustafa.ismail-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
>
> If RTR WQE is posted and QP is flushed, a CQE is
> incorrectly generated for the RTR WQE. Add code
> to look for the RTR and not generate a CQE when
> QP is flushed.
>
> Fixes: 280cfc4b74e6 ("i40iw: user kernel shared files")
> Signed-off-by: Mustafa Ismail <mustafa.ismail-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
> Signed-off-by: Shiraz Saleem <shiraz.saleem-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
> ---
> drivers/infiniband/hw/i40iw/i40iw_uk.c | 13 +++++++++++++
> drivers/infiniband/hw/i40iw/i40iw_user.h | 1 +
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/infiniband/hw/i40iw/i40iw_uk.c b/drivers/infiniband/hw/i40iw/i40iw_uk.c
> index 0aadb7a..28e6d9e 100644
> --- a/drivers/infiniband/hw/i40iw/i40iw_uk.c
> +++ b/drivers/infiniband/hw/i40iw/i40iw_uk.c
> @@ -821,6 +821,18 @@ static enum i40iw_status_code i40iw_cq_poll_completion(struct i40iw_cq_uk *cq,
> I40IW_RING_SET_TAIL(qp->rq_ring, array_idx + 1);
> pring = &qp->rq_ring;
> } else {
> + if (qp->first_sq_wq) {
> + qp->first_sq_wq = 0;
> + if (!wqe_idx && (qp->sq_ring.head == qp->sq_ring.tail)) {
> + I40IW_RING_MOVE_HEAD_NOCHECK(cq->cq_ring);
> + I40IW_RING_MOVE_TAIL(cq->cq_ring);
> + set_64bit_val(cq->shadow_area, 0,
> + I40IW_RING_GETCURRENT_HEAD(cq->cq_ring));
> + memset(info, 0, sizeof(struct i40iw_cq_poll_info));
> + return i40iw_cq_poll_completion(cq, info);
> + }
> + }
> +
> if (info->comp_status != I40IW_COMPL_STATUS_FLUSHED) {
> info->wr_id = qp->sq_wrtrk_array[wqe_idx].wrid;
> info->bytes_xfered = qp->sq_wrtrk_array[wqe_idx].wr_len;
> @@ -988,6 +1000,7 @@ enum i40iw_status_code i40iw_qp_uk_init(struct i40iw_qp_uk *qp,
> I40IW_RING_MOVE_TAIL(qp->sq_ring);
> I40IW_RING_MOVE_HEAD(qp->initial_ring, ret_code);
> qp->swqe_polarity = 1;
> + qp->first_sq_wq = 1;
> qp->swqe_polarity_deferred = 1;
> qp->rwqe_polarity = 0;
>
> diff --git a/drivers/infiniband/hw/i40iw/i40iw_user.h b/drivers/infiniband/hw/i40iw/i40iw_user.h
> index 84be6f1..995b8eb 100644
> --- a/drivers/infiniband/hw/i40iw/i40iw_user.h
> +++ b/drivers/infiniband/hw/i40iw/i40iw_user.h
> @@ -376,6 +376,7 @@ struct i40iw_qp_uk {
> u8 rwqe_polarity;
> u8 rq_wqe_size;
> u8 rq_wqe_size_multiplier;
> + u8 first_sq_wq;
Isn't this supposed to be "bool" and not "u8"?
Thanks
> bool deferred_flag;
> };
>
> --
> 2.8.3
>
> --
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next prev parent reply other threads:[~2017-10-01 6:19 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-30 1:29 [PATCH 0/5] more i40iw fixes Shiraz Saleem
[not found] ` <20170930012942.9128-1-shiraz.saleem-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-09-30 1:29 ` [PATCH 1/5] i40iw: Do not retransmit MPA request after it is ACKed Shiraz Saleem
[not found] ` <20170930012942.9128-2-shiraz.saleem-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-10-01 6:16 ` Leon Romanovsky
[not found] ` <20171001061609.GC2031-U/DQcQFIOTAAJjI8aNfphQ@public.gmane.org>
2017-10-03 3:34 ` Nikolova, Tatyana E
2017-09-30 1:29 ` [PATCH 2/5] i40iw: Do not generate CQE for RTR on QP flush Shiraz Saleem
[not found] ` <20170930012942.9128-3-shiraz.saleem-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
2017-10-01 6:19 ` Leon Romanovsky [this message]
[not found] ` <20171001061928.GD2031-U/DQcQFIOTAAJjI8aNfphQ@public.gmane.org>
2017-10-02 15:12 ` Ismail, Mustafa
2017-09-30 1:29 ` [PATCH 3/5] i40iw: Do not allow posting WR after QP is flushed Shiraz Saleem
2017-09-30 1:29 ` [PATCH 4/5] i40iw: Add missing memory barriers Shiraz Saleem
2017-09-30 1:29 ` [PATCH 5/5] i40iw: Fix port number for query QP Shiraz Saleem
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