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From: Jason Gunthorpe <jgg@nvidia.com>
To: Weihang Li <liweihang@huawei.com>
Cc: <dledford@redhat.com>, <leon@kernel.org>,
	<linux-rdma@vger.kernel.org>, <linuxarm@huawei.com>
Subject: Re: [PATCH for-next 2/3] RDMA/hns: Add new interfaces to set/clear/read fields in QPC
Date: Tue, 6 Oct 2020 16:55:51 -0300	[thread overview]
Message-ID: <20201006195551.GA161726@nvidia.com> (raw)
In-Reply-To: <1601458452-55263-3-git-send-email-liweihang@huawei.com>

On Wed, Sep 30, 2020 at 05:34:11PM +0800, Weihang Li wrote:
> From: Lang Cheng <chenglang@huawei.com>
> 
> For a field in extended QPC, there are four newly added interfaces:
> - hr_reg_set(arr, field) can set all bits to 1,
> - hr_reg_clear(arr, field) can clear all bits to 0,
> - hr_reg_write(arr, field, val) can write a new value,
> - hr_reg_read(arr, field) can read the value.
> 'arr' is the array name of extended QPC, and 'field' is the global bit
> offset of the whole array.
> 
> Signed-off-by: Lang Cheng <chenglang@huawei.com>
> Signed-off-by: Weihang Li <liweihang@huawei.com>
>  drivers/infiniband/hw/hns/hns_roce_common.h | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/drivers/infiniband/hw/hns/hns_roce_common.h b/drivers/infiniband/hw/hns/hns_roce_common.h
> index f5669ff..ab2386d 100644
> +++ b/drivers/infiniband/hw/hns/hns_roce_common.h
> @@ -53,6 +53,32 @@
>  #define roce_set_bit(origin, shift, val) \
>  	roce_set_field((origin), (1ul << (shift)), (shift), (val))
>  
> +#define hr_reg_set(arr, field)                                                 \
> +	((arr)[(field) / 32] |=                                                \
> +	 cpu_to_le32((field##_W) +                                             \
> +		     BUILD_BUG_ON_ZERO((field) / 32 >= ARRAY_SIZE(arr))))
> +
> +#define hr_reg_clear(arr, field)                                               \
> +	((arr)[(field) / 32] &=                                                \
> +	 ~cpu_to_le32((field##_W) +                                            \
> +		      BUILD_BUG_ON_ZERO((field) / 32 >= ARRAY_SIZE(arr))))
> +
> +#define hr_reg_write(arr, field, val)                                          \
> +	do {                                                                   \
> +		BUILD_BUG_ON((field) / 32 >= ARRAY_SIZE(arr));                 \
> +		(arr)[(field) / 32] &= ~cpu_to_le32(field##_W);                \
> +		(arr)[(field) / 32] |= cpu_to_le32(                            \
> +			((u32)(val) << ((field) % 32)) & (field##_W));         \
> +	} while (0)
> +
> +#define hr_reg_read(arr, field)                                                \
> +	(((le32_to_cpu((arr)[(field) / 32]) & (field##_W)) >> (field) % 32) +  \
> +	 BUILD_BUG_ON_ZERO((field) / 32 >= ARRAY_SIZE(arr)))

Why add these functions that are not used?

Jason

  reply	other threads:[~2020-10-06 19:56 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-30  9:34 [PATCH for-next 0/3] RDMA/hns: Add supports for stash Weihang Li
2020-09-30  9:34 ` [PATCH for-next 1/3] RDMA/hns: Add support for CQ stash Weihang Li
2020-09-30  9:34 ` [PATCH for-next 2/3] RDMA/hns: Add new interfaces to set/clear/read fields in QPC Weihang Li
2020-10-06 19:55   ` Jason Gunthorpe [this message]
2020-10-09  2:01     ` liweihang
2020-09-30  9:34 ` [PATCH for-next 3/3] RDMA/hns: Add support for QP stash Weihang Li

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