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Wed, 27 Jan 2021 02:41:10 +0000 Date: Tue, 26 Jan 2021 22:41:09 -0400 From: Jason Gunthorpe To: "Saleem, Shiraz" CC: "dledford@redhat.com" , "kuba@kernel.org" , "davem@davemloft.net" , "linux-rdma@vger.kernel.org" , "gregkh@linuxfoundation.org" , "netdev@vger.kernel.org" , "Ertman, David M" , "Nguyen, Anthony L" , "Ismail, Mustafa" Subject: Re: [PATCH 09/22] RDMA/irdma: Implement HW Admin Queue OPs Message-ID: <20210127024109.GK4147@nvidia.com> References: <20210122234827.1353-1-shiraz.saleem@intel.com> <20210122234827.1353-10-shiraz.saleem@intel.com> <20210125192319.GW4147@nvidia.com> <5c36451841f64f90ac2be6d23ffa9578@intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <5c36451841f64f90ac2be6d23ffa9578@intel.com> X-ClientProxiedBy: MN2PR05CA0063.namprd05.prod.outlook.com (2603:10b6:208:236::32) To DM6PR12MB3834.namprd12.prod.outlook.com (2603:10b6:5:14a::12) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from mlx.ziepe.ca (142.162.115.133) by MN2PR05CA0063.namprd05.prod.outlook.com (2603:10b6:208:236::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3805.7 via Frontend Transport; Wed, 27 Jan 2021 02:41:10 +0000 Received: from jgg by mlx with local (Exim 4.94) (envelope-from ) id 1l4alZ-007KOh-C9; Tue, 26 Jan 2021 22:41:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1611715277; bh=/oHl6y1opY73UQDRpIt+UlaiGJAMUzYncsyt2HojZKg=; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:Date: From:To:CC:Subject:Message-ID:References:Content-Type: Content-Disposition:In-Reply-To:X-ClientProxiedBy:MIME-Version: X-MS-Exchange-MessageSentRepresentingType; b=NY52gJFLf1/uevsRqgkYleJKDFYlgG/1G0cJ5elBu1rHcs4Bl5n1QNEYDUaxTHJzZ a5SLuYf3mJ0pHZvN3a97EoCCBBIbSxIskvNIKyDjQXvCbaZCjOLURUDluEkUKWdh08 HNRKExjnVmQm9h7RkggStUMcoXZudwO+bmqgeSJEy3Rrt4QCZwdUQKD373i+lyRfkS kd6yS1PgdO50OHULtugoAcIgtVOtKPOH+M1zK8xWIZ1A7eJH8Fra4yC+yYmL+wu8/2 NdVhro7KYjSkm7R0EE3l+79ANASHLBn5+nhJCN0nTVJFKPGr4YT1xATpviKtDKn03i KSa7d+8lvDExw== Precedence: bulk List-ID: X-Mailing-List: linux-rdma@vger.kernel.org On Wed, Jan 27, 2021 at 12:41:59AM +0000, Saleem, Shiraz wrote: > > Subject: Re: [PATCH 09/22] RDMA/irdma: Implement HW Admin Queue OPs > > > > On Fri, Jan 22, 2021 at 05:48:14PM -0600, Shiraz Saleem wrote: > > > +#define LS_64_1(val, bits) ((u64)(uintptr_t)(val) << (bits)) > > > +#define RS_64_1(val, bits) ((u64)(uintptr_t)(val) >> (bits)) > > > +#define LS_32_1(val, bits) ((u32)((val) << (bits))) > > > +#define RS_32_1(val, bits) ((u32)((val) >> (bits))) > > > +#define LS_64(val, field) (((u64)(val) << field ## _S) & (field ## _M)) > > > +#define RS_64(val, field) ((u64)((val) & field ## _M) >> field ## _S) > > > +#define LS_32(val, field) (((val) << field ## _S) & (field ## _M)) > > > +#define RS_32(val, field) (((val) & field ## _M) >> field ## _S) > > > > Yikes, why can't this use the normal GENMASK/FIELD_PREP infrastructure like the > > other new drivers are now doing? > > > > EFA is not a perfect example, but EFA_GET/EFA_SET are the macros I would > > expect to see, just without the _MASK thing. > > > > IBA_GET/SET shows how to do that pattern > > > > > +#define FLD_LS_64(dev, val, field) \ > > > + (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## > > _M]) > > > +#define FLD_RS_64(dev, val, field) \ > > > + ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## > > _S]) > > > +#define FLD_LS_32(dev, val, field) \ > > > + (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M]) > > > +#define FLD_RS_32(dev, val, field) \ > > > + ((u64)((val) & (dev)->hw_masks[field ## _M]) >> > > > +(dev)->hw_shifts[field ## _S]) > > > > Is it because the register access is programmable? That shouldn't be a significant > > problem. > > > > Yes. How do we solve that? > > https://lore.kernel.org/linux-rdma/20200602232903.GD65026@mellanox.com/ Ooh, I'm remarkably consistent after all this time I think the answer hasn't changed the point is to make the macros the same. And the LS/RS stuff isn't using the indirection, so why isn't it using normal GENMASK stuff? Jason