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From: Saeed Mahameed <saeed@kernel.org>
To: "David S. Miller" <davem@davemloft.net>,
	Jakub Kicinski <kuba@kernel.org>
Cc: netdev@vger.kernel.org, linux-rdma@vger.kernel.org,
	Roi Dayan <roid@nvidia.com>, Dmytro Linkin <dlinkin@nvidia.com>,
	Saeed Mahameed <saeedm@nvidia.com>
Subject: [net 09/18] net/mlx5e: Check correct ip_version in decapsulation route resolution
Date: Wed, 10 Mar 2021 11:03:33 -0800	[thread overview]
Message-ID: <20210310190342.238957-10-saeed@kernel.org> (raw)
In-Reply-To: <20210310190342.238957-1-saeed@kernel.org>

From: Roi Dayan <roid@nvidia.com>

flow_attr->ip_version has the matching that should be done inner/outer.
When working with chains, decapsulation is done on chain0 and next chain
match on outer header which is the original inner which could be ipv4.
So in tunnel route resolution we cannot use that to know which ip version
we are at so save tun_ip_version when parsing the tunnel match and use
that.

Fixes: a508728a4c8b ("net/mlx5e: VF tunnel RX traffic offloading")
Signed-off-by: Roi Dayan <roid@nvidia.com>
Reviewed-by: Dmytro Linkin <dlinkin@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c       | 8 ++++----
 drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c | 3 ++-
 drivers/net/ethernet/mellanox/mlx5/core/en_tc.h           | 1 +
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c
index f8075a604605..172e0474f2e6 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun.c
@@ -685,14 +685,14 @@ int mlx5e_tc_tun_route_lookup(struct mlx5e_priv *priv,
 	u16 vport_num;
 	int err = 0;
 
-	if (flow_attr->ip_version == 4) {
+	if (flow_attr->tun_ip_version == 4) {
 		/* Addresses are swapped for decap */
 		attr.fl.fl4.saddr = esw_attr->rx_tun_attr->dst_ip.v4;
 		attr.fl.fl4.daddr = esw_attr->rx_tun_attr->src_ip.v4;
 		err = mlx5e_route_lookup_ipv4_get(priv, priv->netdev, &attr);
 	}
 #if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
-	else if (flow_attr->ip_version == 6) {
+	else if (flow_attr->tun_ip_version == 6) {
 		/* Addresses are swapped for decap */
 		attr.fl.fl6.saddr = esw_attr->rx_tun_attr->dst_ip.v6;
 		attr.fl.fl6.daddr = esw_attr->rx_tun_attr->src_ip.v6;
@@ -718,10 +718,10 @@ int mlx5e_tc_tun_route_lookup(struct mlx5e_priv *priv,
 	esw_attr->rx_tun_attr->decap_vport = vport_num;
 
 out:
-	if (flow_attr->ip_version == 4)
+	if (flow_attr->tun_ip_version == 4)
 		mlx5e_route_lookup_ipv4_put(&attr);
 #if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
-	else if (flow_attr->ip_version == 6)
+	else if (flow_attr->tun_ip_version == 6)
 		mlx5e_route_lookup_ipv6_put(&attr);
 #endif
 	return err;
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c
index 6a116335bb21..7f7b0f6dcdf9 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c
@@ -89,6 +89,7 @@ int mlx5e_tc_set_attr_rx_tun(struct mlx5e_tc_flow *flow,
 	 * required to establish routing.
 	 */
 	flow_flag_set(flow, TUN_RX);
+	flow->attr->tun_ip_version = ip_version;
 	return 0;
 }
 
@@ -1091,7 +1092,7 @@ int mlx5e_attach_decap_route(struct mlx5e_priv *priv,
 	if (err || !esw_attr->rx_tun_attr->decap_vport)
 		goto out;
 
-	key.ip_version = attr->ip_version;
+	key.ip_version = attr->tun_ip_version;
 	if (key.ip_version == 4)
 		key.endpoint_ip.v4 = esw_attr->rx_tun_attr->dst_ip.v4;
 	else
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h
index 89003ae7775a..25c091795bcd 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.h
@@ -79,6 +79,7 @@ struct mlx5_flow_attr {
 	u8 inner_match_level;
 	u8 outer_match_level;
 	u8 ip_version;
+	u8 tun_ip_version;
 	u32 flags;
 	union {
 		struct mlx5_esw_flow_attr esw_attr[0];
-- 
2.29.2


  parent reply	other threads:[~2021-03-10 19:04 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-10 19:03 [pull request][net 00/18] mlx5 fixes 2021-03-10 Saeed Mahameed
2021-03-10 19:03 ` [net 01/18] net/mlx5e: Enforce minimum value check for ICOSQ size Saeed Mahameed
2021-03-10 23:40   ` patchwork-bot+netdevbpf
2021-03-10 19:03 ` [net 02/18] net/mlx5e: RX, Mind the MPWQE gaps when calculating offsets Saeed Mahameed
2021-03-10 19:03 ` [net 03/18] net/mlx5e: Accumulate port PTP TX stats with other channels stats Saeed Mahameed
2021-03-10 19:03 ` [net 04/18] net/mlx5e: Set PTP channel pointer explicitly to NULL Saeed Mahameed
2021-03-10 19:03 ` [net 05/18] net/mlx5e: When changing XDP program without reset, take refs for XSK RQs Saeed Mahameed
2021-03-10 19:03 ` [net 06/18] net/mlx5e: Revert parameters on errors when changing PTP state without reset Saeed Mahameed
2021-03-10 19:03 ` [net 07/18] net/mlx5e: Don't match on Geneve options in case option masks are all zero Saeed Mahameed
2021-03-10 19:03 ` [net 08/18] net/mlx5: Fix turn-off PPS command Saeed Mahameed
2021-03-10 19:03 ` Saeed Mahameed [this message]
2021-03-10 19:03 ` [net 10/18] net/mlx5: Disable VF tunnel TX offload if ignore_flow_level isn't supported Saeed Mahameed
2021-03-10 19:03 ` [net 11/18] net/mlx5e: Fix error flow in change profile Saeed Mahameed
2021-03-10 19:03 ` [net 12/18] net/mlx5: Set QP timestamp mode to default Saeed Mahameed
2021-03-10 19:03 ` [net 13/18] RDMA/mlx5: Fix timestamp default mode Saeed Mahameed
2021-03-10 19:25   ` Jason Gunthorpe
2021-03-11  8:58   ` Leon Romanovsky
2021-03-10 19:03 ` [net 14/18] net/mlx5e: E-switch, Fix rate calculation division Saeed Mahameed
2021-03-10 19:03 ` [net 15/18] net/mlx5: SF, Correct vhca context size Saeed Mahameed
2021-03-10 19:03 ` [net 16/18] net/mlx5: SF: Fix memory leak of work item Saeed Mahameed
2021-03-10 19:03 ` [net 17/18] net/mlx5: SF: Fix error flow of SFs allocation flow Saeed Mahameed
2021-03-10 19:03 ` [net 18/18] net/mlx5: DR, Fix potential shift wrapping of 32-bit value in STEv1 getter Saeed Mahameed

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