From: Saeed Mahameed <saeed@kernel.org>
To: "David S. Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>
Cc: netdev@vger.kernel.org, linux-rdma@vger.kernel.org,
Maor Gottlieb <maorg@nvidia.com>,
Saeed Mahameed <saeedm@nvidia.com>
Subject: [net 12/18] net/mlx5: Set QP timestamp mode to default
Date: Wed, 10 Mar 2021 11:03:36 -0800 [thread overview]
Message-ID: <20210310190342.238957-13-saeed@kernel.org> (raw)
In-Reply-To: <20210310190342.238957-1-saeed@kernel.org>
From: Maor Gottlieb <maorg@nvidia.com>
QPs which don't care from timestamp mode, should set the ts_format
to default, otherwise the QP creation could be failed if the timestamp
mode is not supported.
Fixes: 2fe8d4b87802 ("RDMA/mlx5: Fail QP creation if the device can not support the CQE TS")
Signed-off-by: Maor Gottlieb <maorg@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c | 1 +
drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c | 1 +
drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c | 1 +
include/linux/mlx5/qp.h | 7 +++++++
4 files changed, 10 insertions(+)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c b/drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c
index 80da50e12915..bd66ab2af5b5 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/fpga/conn.c
@@ -575,6 +575,7 @@ static int mlx5_fpga_conn_create_qp(struct mlx5_fpga_conn *conn,
MLX5_SET(qpc, qpc, log_sq_size, ilog2(conn->qp.sq.size));
MLX5_SET(qpc, qpc, cqn_snd, conn->cq.mcq.cqn);
MLX5_SET(qpc, qpc, cqn_rcv, conn->cq.mcq.cqn);
+ MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(mdev));
MLX5_SET64(qpc, qpc, dbr_addr, conn->qp.wq_ctrl.db.dma);
if (MLX5_CAP_GEN(mdev, cqe_version) == 1)
MLX5_SET(qpc, qpc, user_index, 0xFFFFFF);
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c
index 756fa0401ab7..6f7cef47e04c 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c
@@ -233,6 +233,7 @@ int mlx5i_create_underlay_qp(struct mlx5e_priv *priv)
}
qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
+ MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(priv->mdev));
MLX5_SET(qpc, qpc, st, MLX5_QP_ST_UD);
MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
MLX5_SET(qpc, qpc, ulp_stateless_offload_mode,
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c
index 83c4c877d558..8a6a56f9dc4e 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c
@@ -169,6 +169,7 @@ static struct mlx5dr_qp *dr_create_rc_qp(struct mlx5_core_dev *mdev,
MLX5_SET(qpc, qpc, log_rq_size, ilog2(dr_qp->rq.wqe_cnt));
MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
MLX5_SET(qpc, qpc, log_sq_size, ilog2(dr_qp->sq.wqe_cnt));
+ MLX5_SET(qpc, qpc, ts_format, mlx5_get_qp_default_ts(mdev));
MLX5_SET64(qpc, qpc, dbr_addr, dr_qp->wq_ctrl.db.dma);
if (MLX5_CAP_GEN(mdev, cqe_version) == 1)
MLX5_SET(qpc, qpc, user_index, 0xFFFFFF);
diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h
index d75ef8aa8fac..b7deb790f257 100644
--- a/include/linux/mlx5/qp.h
+++ b/include/linux/mlx5/qp.h
@@ -547,4 +547,11 @@ static inline const char *mlx5_qp_state_str(int state)
}
}
+static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
+{
+ return !MLX5_CAP_ROCE(dev, qp_ts_format) ?
+ MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
+ MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
+}
+
#endif /* MLX5_QP_H */
--
2.29.2
next prev parent reply other threads:[~2021-03-10 19:04 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-10 19:03 [pull request][net 00/18] mlx5 fixes 2021-03-10 Saeed Mahameed
2021-03-10 19:03 ` [net 01/18] net/mlx5e: Enforce minimum value check for ICOSQ size Saeed Mahameed
2021-03-10 23:40 ` patchwork-bot+netdevbpf
2021-03-10 19:03 ` [net 02/18] net/mlx5e: RX, Mind the MPWQE gaps when calculating offsets Saeed Mahameed
2021-03-10 19:03 ` [net 03/18] net/mlx5e: Accumulate port PTP TX stats with other channels stats Saeed Mahameed
2021-03-10 19:03 ` [net 04/18] net/mlx5e: Set PTP channel pointer explicitly to NULL Saeed Mahameed
2021-03-10 19:03 ` [net 05/18] net/mlx5e: When changing XDP program without reset, take refs for XSK RQs Saeed Mahameed
2021-03-10 19:03 ` [net 06/18] net/mlx5e: Revert parameters on errors when changing PTP state without reset Saeed Mahameed
2021-03-10 19:03 ` [net 07/18] net/mlx5e: Don't match on Geneve options in case option masks are all zero Saeed Mahameed
2021-03-10 19:03 ` [net 08/18] net/mlx5: Fix turn-off PPS command Saeed Mahameed
2021-03-10 19:03 ` [net 09/18] net/mlx5e: Check correct ip_version in decapsulation route resolution Saeed Mahameed
2021-03-10 19:03 ` [net 10/18] net/mlx5: Disable VF tunnel TX offload if ignore_flow_level isn't supported Saeed Mahameed
2021-03-10 19:03 ` [net 11/18] net/mlx5e: Fix error flow in change profile Saeed Mahameed
2021-03-10 19:03 ` Saeed Mahameed [this message]
2021-03-10 19:03 ` [net 13/18] RDMA/mlx5: Fix timestamp default mode Saeed Mahameed
2021-03-10 19:25 ` Jason Gunthorpe
2021-03-11 8:58 ` Leon Romanovsky
2021-03-10 19:03 ` [net 14/18] net/mlx5e: E-switch, Fix rate calculation division Saeed Mahameed
2021-03-10 19:03 ` [net 15/18] net/mlx5: SF, Correct vhca context size Saeed Mahameed
2021-03-10 19:03 ` [net 16/18] net/mlx5: SF: Fix memory leak of work item Saeed Mahameed
2021-03-10 19:03 ` [net 17/18] net/mlx5: SF: Fix error flow of SFs allocation flow Saeed Mahameed
2021-03-10 19:03 ` [net 18/18] net/mlx5: DR, Fix potential shift wrapping of 32-bit value in STEv1 getter Saeed Mahameed
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