Re: [PATCH net-next 3/7] qed: Add support for RoCE hw init

Bjorn Helgaas
2022-10-10T21:44:49Z

[ping, updated Ariel's address]

On Fri, Oct 07, 2022 at 10:48:32AM -0500, Bjorn Helgaas wrote:
> On Sat, Oct 01, 2016 at 09:59:57PM +0300, Yuval Mintz wrote:
> > From: Ram Amrani <Ram.Amrani@caviumnetworks.com>
> >
> > This adds the backbone required for the various HW initalizations
> > which are necessary for the qedr driver - FW notification, resource
> > initializations, etc.
> > ...
>
> > diff --git a/drivers/net/ethernet/qlogic/qed/qed_roce.c b/drivers/net/ethernet/qlogic/qed/qed_roce.c
> > ...
> > + /* Check atomic operations support in PCI configuration space. */
> > + pci_read_config_dword(cdev->pdev,
> > + cdev->pdev->pcie_cap + PCI_EXP_DEVCTL2,
> > + &pci_status_control);
> > +
> > + if (pci_status_control & PCI_EXP_DEVCTL2_LTR_EN)
> > + SET_FIELD(dev->dev_caps, QED_RDMA_DEV_CAP_ATOMIC_OP, 1);
>
> I don't understand this.
>
> 1) PCI_EXP_DEVCTL2 is a 16-bit register ("word"), not a 32-bit one
> ("dword").
>
> 2) QED_RDMA_DEV_CAP_ATOMIC_OP is set here but is not read anywhere
> in this patch. Is it used by the qed device itself?
>
> 3) PCI_EXP_DEVCTL2_LTR_EN is for Latency Tolerance Reporting and is
> not related to atomic ops. I don't know what
> QED_RDMA_DEV_CAP_ATOMIC_OP means, but possibly one of these was
> intended instead?
>
> - PCI_EXP_DEVCAP2_ATOMIC_COMP32 means the device supports 32-bit
> AtomicOps as a completer.
> - PCI_EXP_DEVCAP2_ATOMIC_COMP64 means the device supports 64-bit
> AtomicOps as a completer.
> - PCI_EXP_DEVCAP2_ATOMIC_COMP128 means the device supports 128-bit
> AtomicOps as a completer.
> - PCI_EXP_DEVCTL2_ATOMIC_REQ means the device is allowed to
> initiate AtomicOps.
>
> (This code is now in qed_rdma.c)