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Miller" , Jakub Kicinski , Paolo Abeni , Eric Dumazet , Andrew Lunn CC: Saeed Mahameed , Tariq Toukan , "Leon Romanovsky" , , , , Chris Mi , Roi Dayan , Maor Gottlieb , Mark Bloch Subject: [PATCH net 5/5] net/mlx5: E-switch, Fix error handling for enabling roce Date: Wed, 23 Apr 2025 11:36:11 +0300 Message-ID: <20250423083611.324567-6-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250423083611.324567-1-mbloch@nvidia.com> References: <20250423083611.324567-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF00006001:EE_|DS0PR12MB9059:EE_ X-MS-Office365-Filtering-Correlation-Id: 438e063d-4e2a-41c3-ea93-08dd8242008f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?zyv4gYEHWm0V8XQPXtp547JDcMvAGDI/wNWq5AsO8lnIv2ngRCMYbfeJ7hnI?= =?us-ascii?Q?mQGQ/ll2Qj6aFhyQ28zEGVrOvq0p/9uwY2s30jHqhY1h7EFrv3ZgaGLHnsiR?= =?us-ascii?Q?wQV3FSHI1NpWfW8kmfPMouu/2zVvzyK1RCzXEyHnr8bc0AQ9T5YTGA6oB0q0?= =?us-ascii?Q?Q+HYTYUNZ52SkWqo0yqPSlqqXVpnBMTW38w/5xFKF/iySOVsekmSDr/dwOKQ?= =?us-ascii?Q?ZkdjQGgh/vuwIlJzml2bH3+DzzRSkDaYnj5Ol3jOH6yB1pEnxXyXCpkqIF/q?= =?us-ascii?Q?3PznMEar/j27Xh1AYGoczs3U5Cw4RJCX9psb0fTkq/oy1ONMT/mTOSMIdktk?= =?us-ascii?Q?HRKSy9FWl6znf9q9aMGag0N2FKg/xSwFio+KtD4n3o2oUqtZOLYS/agkR3Dr?= =?us-ascii?Q?jM/Vs4PKbYapli6QcSsQVoH5kGWx2ggME8kw8E7wzchvOk8vtu6jsKZ848XB?= =?us-ascii?Q?85mdB1XbGso6eCGLcvIkny5C4c6GPjSNdnV9rSf3xyXbvLCoxGFZJr697KLt?= =?us-ascii?Q?X6PTyQvBF6s+XbmeC/ElkjUl0S0IhnspGllMYXmCg9cnu9hj0CkTy8XDUG0T?= =?us-ascii?Q?gqcfwomX+QEogFrgZrsG124gTKyoikzFG6uNulv3NMQ1AtWxI910eQW59Qnd?= =?us-ascii?Q?x0WS47ITACXArDi1MbuzJdQExTv5NZqY7lrirSoc4uhwFreOPAmgWxUT1e8N?= =?us-ascii?Q?yWaXgR3ihTfDUg9hi1+RmnQWD6sKhssdYndBD4gfLYmNOTokKTacRpThJdxh?= =?us-ascii?Q?BdMYVLK2A7PICFcS06Lo4N9sDyeglb+nTnskK59lk9Uyk2IWg3jlN5wOey3i?= =?us-ascii?Q?KAzGbA40Ml3sFbMEVcLFxwmpNhVzO/dczh0j0dT2qtV5HkziScRqqyiw+Vwk?= =?us-ascii?Q?Mes0sPNHcL8mJuUDq0T8/ARGYJCr8EQyPpMh+6jUa1/kK8efhEcEsIWtP6Yy?= =?us-ascii?Q?tuyCfKKp+5tWqnOpwo2A3YtHmfVdopj96QbGQSAS9bN/CPcWZihnpq5GLkuV?= =?us-ascii?Q?jrAlcLThIpxX0+S4bshW9b+A/z+eATSSxjrd7Ea1KANkDarxFtTcS5Iiq8oP?= =?us-ascii?Q?kQycLSggp0RTVoHzgFvT/32fvzl4GpUD/FdlmTwokc1CTBRQO3t+qTmQfnVv?= =?us-ascii?Q?IxLUZYP5NCtya0qQcx6i+pamXPlLTmnNVZtGpi7cs+lCttYDNwRSNrXxZFfs?= =?us-ascii?Q?Bx+RRxO6FEskKjrFW2IzhKJ5c3dN7n3J9ox8/NLxyLAS/VD6p1sG29zKu+vc?= =?us-ascii?Q?kzeFc4PZN/Enmufs84hdsCiaWxATdlaZwUAmOOAgqjMOLa9fLLahc5dTiBM+?= =?us-ascii?Q?lg7b4jiqnaRmKxkK9Ab8IeCUE8QDAPfJyFuUnJciKmmIxXUvM+dC1IAtJief?= =?us-ascii?Q?Y9AwnZA0Tb1zkCKPF6KTr5fscw2g0bQyFxrNx6pakTzajM4zgOxn/tMJOgBz?= =?us-ascii?Q?bycbkP3i22xVx1VS2LvWJziTtQe8MqPvJWs+pciYEPLo51vI4S7QeskMKwEy?= =?us-ascii?Q?Bj92B89KuaO9d7XsXcZfJlfmRP/bryAVV3fB?= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2025 08:36:54.3487 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 438e063d-4e2a-41c3-ea93-08dd8242008f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00006001.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB9059 From: Chris Mi The cited commit assumes enabling roce always succeeds. But it is not true. Add error handling for it. Fixes: 80f09dfc237f ("net/mlx5: Eswitch, enable RoCE loopback traffic") Signed-off-by: Chris Mi Reviewed-by: Roi Dayan Reviewed-by: Maor Gottlieb Signed-off-by: Mark Bloch --- .../net/ethernet/mellanox/mlx5/core/eswitch_offloads.c | 5 ++++- drivers/net/ethernet/mellanox/mlx5/core/rdma.c | 9 +++++---- drivers/net/ethernet/mellanox/mlx5/core/rdma.h | 4 ++-- 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c index a6a8eea5980c..0e3a977d5332 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch_offloads.c @@ -3533,7 +3533,9 @@ int esw_offloads_enable(struct mlx5_eswitch *esw) int err; mutex_init(&esw->offloads.termtbl_mutex); - mlx5_rdma_enable_roce(esw->dev); + err = mlx5_rdma_enable_roce(esw->dev); + if (err) + goto err_roce; err = mlx5_esw_host_number_init(esw); if (err) @@ -3594,6 +3596,7 @@ int esw_offloads_enable(struct mlx5_eswitch *esw) esw_offloads_metadata_uninit(esw); err_metadata: mlx5_rdma_disable_roce(esw->dev); +err_roce: mutex_destroy(&esw->offloads.termtbl_mutex); return err; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/rdma.c b/drivers/net/ethernet/mellanox/mlx5/core/rdma.c index f585ef5a3424..5c552b71e371 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/rdma.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/rdma.c @@ -140,17 +140,17 @@ void mlx5_rdma_disable_roce(struct mlx5_core_dev *dev) mlx5_nic_vport_disable_roce(dev); } -void mlx5_rdma_enable_roce(struct mlx5_core_dev *dev) +int mlx5_rdma_enable_roce(struct mlx5_core_dev *dev) { int err; if (!MLX5_CAP_GEN(dev, roce)) - return; + return 0; err = mlx5_nic_vport_enable_roce(dev); if (err) { mlx5_core_err(dev, "Failed to enable RoCE: %d\n", err); - return; + return err; } err = mlx5_rdma_add_roce_addr(dev); @@ -165,10 +165,11 @@ void mlx5_rdma_enable_roce(struct mlx5_core_dev *dev) goto del_roce_addr; } - return; + return err; del_roce_addr: mlx5_rdma_del_roce_addr(dev); disable_roce: mlx5_nic_vport_disable_roce(dev); + return err; } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/rdma.h b/drivers/net/ethernet/mellanox/mlx5/core/rdma.h index 750cff2a71a4..3d9e76c3d42f 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/rdma.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/rdma.h @@ -8,12 +8,12 @@ #ifdef CONFIG_MLX5_ESWITCH -void mlx5_rdma_enable_roce(struct mlx5_core_dev *dev); +int mlx5_rdma_enable_roce(struct mlx5_core_dev *dev); void mlx5_rdma_disable_roce(struct mlx5_core_dev *dev); #else /* CONFIG_MLX5_ESWITCH */ -static inline void mlx5_rdma_enable_roce(struct mlx5_core_dev *dev) {} +static inline int mlx5_rdma_enable_roce(struct mlx5_core_dev *dev) { return 0; } static inline void mlx5_rdma_disable_roce(struct mlx5_core_dev *dev) {} #endif /* CONFIG_MLX5_ESWITCH */ -- 2.34.1