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Wed, 3 Jun 2026 03:27:18 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Jiri Pirko , Simon Horman , "Jonathan Corbet" , Shuah Khan , "Saeed Mahameed" , Leon Romanovsky , Tariq Toukan , Mark Bloch , Vlad Dumitrescu , Daniel Zahka , "Aleksandr Loktionov" , Przemek Kitszel , Arthur Kiyanovski , "Petr Machata" , Ratheesh Kannoth , "Nikolay Aleksandrov" , David Ahern , , , , , Gal Pressman , Amery Hung , Nikolay Aleksandrov Subject: [PATCH net-next V3 2/2] net/mlx5: implement max_sfs parameter Date: Wed, 3 Jun 2026 13:26:46 +0300 Message-ID: <20260603102646.404797-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260603102646.404797-1-tariqt@nvidia.com> References: <20260603102646.404797-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000A672F:EE_|SJ2PR12MB7866:EE_ X-MS-Office365-Filtering-Correlation-Id: fc1e5e8b-bdd2-4206-5067-08dec15abe6e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|36860700016|82310400026|376014|6133799003|18002099003|3023799007|11063799006|22082099003|56012099006; X-Microsoft-Antispam-Message-Info: 9uiDewN8CyoB4FaxGQu7yHkRzuUW1aIznvp9JJf8vHYPENQKlQHkWJRVqNlPjDdj8KTOq1OeqP4V2CTz3KuNilJIanu0DPverTP1F6hfgkGjU/o9brnz1bBxl1z8/sMHg7LjvkTi0IEdKKP1S9gpN27+EYSOaphaMqM4agKA9TVSrG9w5Ms6j167aR0nDYsX2EmfePY9kjoxHcZrfGHPOH7IJSh3AdUKbSw4nmfOHwyL6KU6J9SVdDUGoqSYXJ8MjQpZ6A2Mr8Mi+Gyf4Iasm1AESrSO1PIMH6eREC8UwNvl5JyUmpdhebG1OOg1P7nJg1jV272yOaaJYuInBgQjIIUZs7WmQ8oODKFJPBipM6As6n+Cp35p/mQdNWlVMGhXe1y9YHrNOCYXp1YkyASDxCHXAKDXqbcYmCoCPw6Ivws6Q8tIDCdNQJZZGbWG3mNI4IfY9Zo5doSZRBbHwM9sWrkApU5Fz6kVhvogsJFHw3nlllx/5rRFFjKhOdHnsCiQ0NQakFpMJqS3E/AubiZKzqE1wVMIPW7OCafj+fTYI26EIAPJYswApNYUinO2et8I8B/IWtCLH1IofbtmlnGWlVd7iTJWKzD+Fes+BJn9m7K4FGAJ50B0dILpxzhIIgzpkC4RQ0pevBt9IIu2A/ognc3tcS0hvrEBU8bzV7KEwWX9S0WXQ6Z0xNx3uiByEkT+wt5X8xt0zGhEZJ7FUYOwmRks9wgsWYBSe04w8LCL9tI= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(36860700016)(82310400026)(376014)(6133799003)(18002099003)(3023799007)(11063799006)(22082099003)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VD1DdI1S2iCQDEmTJjcC/ghJLAWjclBvYrbvkpetW+JKPMoHC/dv+KaRgfZqmblAyKlmF1PBf4PVZFZEyJONle84ekSXybSXmfloZvO9/UsBvIYGvLnAAEQT0Yfn3T3+y0uI+xwCUR7OONe4N+BSCUlAmwU7v58k6xOiTttDT/HFtGn8r62EvI/moj6DpMlKfIaBpggUwvKTkbrTzwDYvLXISyoTzJHEUfIhTadyks26LTrr+pN+HO7IbPO2Xqi37T4GUFezyd6n04IhAvMBCv0QuVhuX3Kg0QHi1MXYUYUsoeqz+yG20LhXS0ZtXE46N01zDD906ay9HA1ZlAy63Pob2q7gzkZiaLr+8cJdvcKLqeynCPl7xLZNfj6YZ5Yf5ZJcp6rL1NzuX8qmDRVioOT7q+kpBTd1ry/nK3jjX91J8Q8PU4xxO7YRnrAjg9fi X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jun 2026 10:27:41.7855 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc1e5e8b-bdd2-4206-5067-08dec15abe6e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A672F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7866 From: Nikolay Aleksandrov Implement max_sfs generic parameter to allow users to control the total light-weight NIC subfunctions that can be created using devlink instead of external vendor tools. A value of 0 will effectively disable creation of new subfunction devices. A warning is sent to user-space via extack (returning extack without error code is interpreted as a warning by user-space tools). The maximum value is capped at U16_MAX. Signed-off-by: Nikolay Aleksandrov Reviewed-by: David Ahern Signed-off-by: Tariq Toukan --- Documentation/networking/devlink/mlx5.rst | 7 +- .../mellanox/mlx5/core/lib/nv_param.c | 118 +++++++++++++++++- 2 files changed, 121 insertions(+), 4 deletions(-) diff --git a/Documentation/networking/devlink/mlx5.rst b/Documentation/networking/devlink/mlx5.rst index 4bba4d780a4a..f5e2dccafa5a 100644 --- a/Documentation/networking/devlink/mlx5.rst +++ b/Documentation/networking/devlink/mlx5.rst @@ -45,8 +45,13 @@ Parameters - The range is between 1 and a device-specific max. - Applies to each physical function (PF) independently, if the device supports it. Otherwise, it applies symmetrically to all PFs. + * - ``max_sfs`` + - permanent + - The range is between 0 and a device-specific max. + - Applies to each physical function (PF) independently. -Note: permanent parameters such as ``enable_sriov`` and ``total_vfs`` require FW reset to take effect +Note: permanent parameters such as ``enable_sriov``, ``total_vfs`` and ``max_sfs`` + require FW reset to take effect .. code-block:: bash diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c index 4a7275e8b62e..899167a5cd92 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c @@ -68,7 +68,9 @@ struct mlx5_ifc_mnvda_reg_bits { struct mlx5_ifc_nv_global_pci_conf_bits { u8 sriov_valid[0x1]; - u8 reserved_at_1[0x10]; + u8 reserved_at_1[0xa]; + u8 per_pf_num_sf[0x1]; + u8 reserved_at_c[0x5]; u8 per_pf_total_vf[0x1]; u8 reserved_at_12[0xe]; @@ -93,9 +95,11 @@ struct mlx5_ifc_nv_global_pci_cap_bits { }; struct mlx5_ifc_nv_pf_pci_conf_bits { - u8 reserved_at_0[0x9]; + u8 log_sf_bar_size[0x8]; + u8 pf_total_sf_en[0x1]; u8 pf_total_vf_en[0x1]; - u8 reserved_at_a[0x16]; + u8 reserved_at_a[0x6]; + u8 total_sf[0x10]; u8 reserved_at_20[0x20]; @@ -158,6 +162,8 @@ struct mlx5_ifc_nv_sw_accelerate_conf_bits { #define MLX5_GET_CFG_HDR_LEN(_mnvda_ptr) \ MLX5_GET(mnvda_reg, _mnvda_ptr, configuration_item_header.length) +#define MLX5_DEFAULT_LOG_SF_BAR_SIZE 12 + static int mlx5_nv_param_read(struct mlx5_core_dev *dev, void *mnvda, size_t len) { @@ -755,6 +761,108 @@ static int mlx5_devlink_total_vfs_validate(struct devlink *devlink, u32 id, return 0; } +static int mlx5_devlink_max_sfs_get(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx, + struct netlink_ext_ack *extack) +{ + struct mlx5_core_dev *dev = devlink_priv(devlink); + u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {}; + void *data; + int err; + + err = mlx5_nv_param_read_global_pci_conf(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to read global PCI configuration"); + return err; + } + + data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data); + if (!MLX5_GET(nv_global_pci_conf, data, per_pf_num_sf)) { + ctx->val.vu32 = 0; + return 0; + } + + memset(mnvda, 0, sizeof(mnvda)); + err = mlx5_nv_param_read_per_host_pf_conf(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, "Failed to read PF configuration"); + return err; + } + + data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data); + if (MLX5_GET(nv_pf_pci_conf, data, pf_total_sf_en)) + ctx->val.vu32 = MLX5_GET(nv_pf_pci_conf, data, total_sf); + else + ctx->val.vu32 = 0; + + return 0; +} + +static int mlx5_devlink_max_sfs_validate(struct devlink *devlink, u32 id, + union devlink_param_value val, + struct netlink_ext_ack *extack) +{ + if (val.vu32 > U16_MAX) { + NL_SET_ERR_MSG_FMT_MOD(extack, + "Max SFs allowed value is %u", U16_MAX); + return -EINVAL; + } + + return 0; +} + +static int mlx5_devlink_max_sfs_set(struct devlink *devlink, u32 id, + struct devlink_param_gset_ctx *ctx, + struct netlink_ext_ack *extack) +{ + struct mlx5_core_dev *dev = devlink_priv(devlink); + u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {}; + void *data; + int err; + + err = mlx5_nv_param_read_global_pci_conf(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to read global PCI configuration"); + return err; + } + + data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data); + MLX5_SET(nv_global_pci_conf, data, per_pf_num_sf, !!ctx->val.vu32); + + err = mlx5_nv_param_write(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to change per_pf_num_sf global PCI configuration"); + return err; + } + + memset(mnvda, 0, sizeof(mnvda)); + err = mlx5_nv_param_read_per_host_pf_conf(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, "Failed to read PF configuration"); + return err; + } + + data = MLX5_ADDR_OF(mnvda_reg, mnvda, configuration_item_data); + MLX5_SET(nv_pf_pci_conf, data, log_sf_bar_size, + ctx->val.vu32 ? MLX5_DEFAULT_LOG_SF_BAR_SIZE : 0); + MLX5_SET(nv_pf_pci_conf, data, pf_total_sf_en, !!ctx->val.vu32); + MLX5_SET(nv_pf_pci_conf, data, total_sf, ctx->val.vu32); + + err = mlx5_nv_param_write(dev, mnvda, sizeof(mnvda)); + if (err) { + NL_SET_ERR_MSG_MOD(extack, + "Failed to change PF PCI configuration"); + return err; + } + NL_SET_ERR_MSG(extack, + "Modifying max_sfs requires a FW reset and PCI bus rescan"); + + return 0; +} + static const struct devlink_param mlx5_nv_param_devlink_params[] = { DEVLINK_PARAM_GENERIC(ENABLE_SRIOV, BIT(DEVLINK_PARAM_CMODE_PERMANENT), mlx5_devlink_enable_sriov_get, @@ -763,6 +871,10 @@ static const struct devlink_param mlx5_nv_param_devlink_params[] = { mlx5_devlink_total_vfs_get, mlx5_devlink_total_vfs_set, mlx5_devlink_total_vfs_validate), + DEVLINK_PARAM_GENERIC(MAX_SFS, BIT(DEVLINK_PARAM_CMODE_PERMANENT), + mlx5_devlink_max_sfs_get, + mlx5_devlink_max_sfs_set, + mlx5_devlink_max_sfs_validate), DEVLINK_PARAM_DRIVER(MLX5_DEVLINK_PARAM_ID_CQE_COMPRESSION_TYPE, "cqe_compress_type", DEVLINK_PARAM_TYPE_STRING, BIT(DEVLINK_PARAM_CMODE_PERMANENT), -- 2.44.0