From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011007.outbound.protection.outlook.com [40.107.208.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C774548BD55; Wed, 3 Jun 2026 19:33:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.208.7 ARC-Seal:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780515216; cv=fail; b=tlEkPWWwRSjVcQHNadtpssck5XYVC7T86iLVAJberfM/T4B479gGFKV8jFDycLyWyBlgatgTA7kSI4piVxR9zknAXNap9MoI0S800xQbaE4pXbKRbjyawzC8NeFVxXaaxi7ZaavcKvqKoijPDWWiNQYWDclO5s2fVKRXpdcQnLI= ARC-Message-Signature:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1780515216; c=relaxed/simple; bh=onO2pG1AEH3vk27xBQ4d1w+ps68z6VOvlyQl5+tp9go=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=cE1BTK8ORF4srcOAQHEhXJLVM3AvYvKholFdSTgBh1co/pUfGJlwNA0Gs+0P18KVJ6hJZRXVQN/t4Pot4EgJc4Q46N6VBDfDAmOs1x0EHK3aQRs/8J2pY0JVVtvknWvaDDSg7tjPu1bMszw/gdUaQc5JksVv7HfYYOP6mIHMNVU= ARC-Authentication-Results:i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ROJTpzrr; arc=fail smtp.client-ip=40.107.208.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ROJTpzrr" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=o4eiOqq+u1w5OEkf3XlOmT/EPXEW6224bmgZgaiptRl+bt+4GDmkqCdjv/EW0UzDO02Wrb05zLT+nrjxdLbjdvCOlCP9Gn5HfKAcHxJCHvRjgLvlmg/MV0aHkGDJ7zCFb/kB6np1F8EmqkEPYtB/nkCpYEND9nxH5TWczYJmjX3B+sH4b6oRVgBYS9FnvhDlZ2oVqJ75fH64K5i4noa9M7qwo+4SY340rldSDbO45BY5JOKFy8UlexiGwiwz/ijhoUpFOPgepm/vf5/LjGLixDEHU/SYeCar/7YwY7O8GnfI4E8zug9Pe6lw8br/nfc7l7aIuH+F1LrWWQkEPmhp8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=GGwiBNv0ml5gByeB1UQLpeEIeyial0/9QwM1CoFdU1s=; b=jNXukeDF3xI+FIh45mpOIAYzzvDlDfe79XBrBRptbqtWsB6ytb1WbmjfYoKgpF1TFAiP8E70JcxQZQ3fbAoRb8+kQ4hESfuAaisjDmpOirSGuB1uuugr0SSksPVsjub6HP8JVlS9yaLzBLiC7WP2E0D04HvuN9/shjjzxPqxA3WiP6kDO222UNH4JDFVNUbhnGR6Hr00STaogHwqhIIExgrZKNmRThlJiqLxxmPhUlsbyITYznaZMQTlbNG+nhlamm6dTH6Y/uUN7NCxwP6ujcAKS/QJZVaB0qd+qbnNzBchgFvjvK9dfgF7xJQMMgNkYD/UTGD4bupWSMBm1mAW2w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.118.233) smtp.rcpttodomain=google.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=GGwiBNv0ml5gByeB1UQLpeEIeyial0/9QwM1CoFdU1s=; b=ROJTpzrrg9NZmFKXpq/zoerm8kuHhglmWEEOPX11VxlmXiB09Fs4Nv2l53uCf8pNSF37/NF9gpyuCd03eMT3ga5AsLOCSd/sMIKICnoGOb8xU2cweOOwZtoZFruLik+qHgEfV7TO/d0ITxzdbO19K/OJoJtV6jImn+4u67dTlIaWgXK4HY7InBzIdEHzXEkmo1OV6GDNiKsXCEkmvYxczUgY3R1bF8TYYtYJqJk/tGLWnXCjCAAlzkrUdtq9nYCSNEFgUbEhLX6jcMciipC72GPpna3RyBS7qpEflUvJo1q/0Jq4K4Bb/48XguIEHyU6fqszhEK21Au7SbmB8QhXXg== Received: from SJ0PR03CA0004.namprd03.prod.outlook.com (2603:10b6:a03:33a::9) by LV8PR12MB9406.namprd12.prod.outlook.com (2603:10b6:408:20b::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.92.7; Wed, 3 Jun 2026 19:33:26 +0000 Received: from CO1PEPF000066ED.namprd05.prod.outlook.com (2603:10b6:a03:33a:cafe::7e) by SJ0PR03CA0004.outlook.office365.com (2603:10b6:a03:33a::9) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.92.7 via Frontend Transport; Wed, 3 Jun 2026 19:33:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.118.233) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.118.233 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.118.233; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.118.233) by CO1PEPF000066ED.mail.protection.outlook.com (10.167.249.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.92.5 via Frontend Transport; Wed, 3 Jun 2026 19:33:24 +0000 Received: from drhqmail203.nvidia.com (10.126.190.182) by mail.nvidia.com (10.127.129.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 3 Jun 2026 12:33:10 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail203.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 3 Jun 2026 12:33:10 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.2562.20 via Frontend Transport; Wed, 3 Jun 2026 12:33:01 -0700 From: Mark Bloch To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Jonathan Corbet , Shuah Khan , Jiri Pirko , Simon Horman , Sunil Goutham , Linu Cherian , Geetha sowjanya , hariprasad , Subbaraya Sundeep , Bharat Bhushan , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Borislav Petkov (AMD)" , Andrew Morton , Randy Dunlap , "Peter Zijlstra (Intel)" , Thomas Gleixner , Petr Mladek , Tejun Heo , Vlastimil Babka , Feng Tang , Dave Hansen , Christian Brauner , Dapeng Mi , Kees Cook , Marco Elver , Eric Biggers , Li RongQing , "Paul E. McKenney" , "Ethan Nelson-Moore" , , , , Subject: [PATCH net-next V2 0/7] devlink: Add boot-time eswitch mode defaults Date: Wed, 3 Jun 2026 22:32:52 +0300 Message-ID: <20260603193259.3412464-1-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066ED:EE_|LV8PR12MB9406:EE_ X-MS-Office365-Filtering-Correlation-Id: d5d0445c-7100-4766-a352-08dec1a6fa55 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|7416014|36860700016|13003099007|18002099003|6133799003|56012099006|11063799006|3023799007; X-Microsoft-Antispam-Message-Info: Drsn5poAL82PIaBkXOyUQrjkh3g5CbMLTEqWKuFbCxIWG6IhkNLRlE/vSYrU0/nloO6wB4ntZlsiz75XbIZdWmW5NySYJjgNmsrHKfa0EPelxhuYNxA/1iKYSOlZV0RoAk7o809B2rcKug6s7qINArr3xiHfhqM3yhy/Yjh55v4kgkPDW2sAwR/P9gsULTng10seRbuuE6zpvXi+S48m3umAkUFAY9Zwl7diUYphJI9VzfGTJfPO45rzEmlQoz2ziu+dyemMSLMhLCIB0CkYpruwigC3ZUAPF6RRzxsiNxwWkd0tN020SwURtrRKE6gUHn7yp2Cfn/aJ03s+xwnUJgQB9qL364BffkIraSGqoztQE4mOWpyt9+SLa4Y9dxcYXIBcJ/1Rg1Rmfq7ityjq3CY55ci0mQkLaJMi1oKZDfHxOCtu86SGcYt0xAYCsQ6WoQooV8yxKIQ830kS6ZorqyDWZlR5erB7oJ9CFUjuiAfnfJ8ZXQgbDaiVE3C7avQMOLwmbhALt7y8w2X4KPT062kfI8L7u3iUAXBwC97ShuSWO9OA4LzOPjJexaaLhucxhr9wV0oMd3aP29P6HX532AA4O+0ZojU0Uofc2CNsRi9RUE5HKkg+o09U6FIoMEe8XOEB7PHvBvq6RmeocJU3tOtjnBdIK4TAZ7QZjPqvHgdoWbojAsEhJYk2eOKmweDCjHKH+6qVBGoYmynostmhItGJMW99RDRtIPYXie8w+uk= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(7416014)(36860700016)(13003099007)(18002099003)(6133799003)(56012099006)(11063799006)(3023799007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2757K8R+vN72yoPLlr88RsfpkJKmq5lsI7SH0XmRUlr4rAf1YBcQFwRE62SpeV+YDvqbasp6kwGDbN7ggukLHPGE7OYlUssh3PjmxoF+wDf8wZSpjCy5u0T7ruKP+kqWGiIanIAmlWl5GtK6ix5fUoSVkYmxQ+JWYDlIst4vP07ub57TYVSS+14lmvw/sy5raUCnN8QYkdyoZh5e1hrxv55QpyqDX546sEYUhLU1Yy9CanMmoBQx6UYpiDlVfoP7HprsEd1sNChIxZnCSut63CZORyMxrvIxxaB0eQpVCfZpdgE59PiWW4Q2HZdePGEfXhuOsDnHhSa/hPD5PlsOiDKnuMSrgkiYq3vYEKmWV8CsKHamClzHbLiABH3JVgIVpXJX8ulLiOOxvj86AfSFtxwN1Fhc3dY2DHOian2u7tL56iWl20gjCEZHGLNbUtkb X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jun 2026 19:33:24.1165 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d5d0445c-7100-4766-a352-08dec1a6fa55 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9406 This series adds a devlink_eswitch_mode= kernel command line parameter for applying a default devlink eswitch mode during device initialization. Following the discussion with Jakub[1] and the feedback on the RFC postings, this version keeps the scope limited to a boot-time devlink eswitch mode default only. The option selects either all devlink handles or an explicit comma separated handle list: devlink_eswitch_mode=[*]:switchdev devlink_eswitch_mode=[pci/0000:08:00.0,pci/0000:09:00.1]:switchdev_inactive The supported modes are legacy, switchdev and switchdev_inactive. The selected mode is applied through the existing eswitch_mode_set() devlink operation, the same operation used by the devlink eswitch mode command. The preparatory patches move registration points that expose the devlink instance before the driver is ready for a registration-time eswitch mode change. Where registration is moved later, the matching unregister path is moved earlier so unregister notifications are sent from devl_unregister() before object teardown. The final patch adds the parser and applies the default from devlink core when a matching instance is registered and after a successful devlink reload that performed DRIVER_REINIT. Patch 1 skips devlink health recovery notifications while a devlink instance is not registered. Health state and counters are still updated, but there is no registered instance for userspace to observe or receive notifications from yet. This lets drivers move registration later without hitting health notification registration assertions during early initialization. Patch 2 moves netdevsim devlink registration after device initialization, so registration-time defaults can call eswitch_mode_set() after simulator state is ready. It also unregisters devlink before netdevsim tears down the objects that were registered before devlink became visible. Patch 3 clears the mlx5 FW reset-in-progress bit before reloading after a firmware reset. Patch 4 moves mlx5 devlink registration after device initialization, including the lightweight init path, and moves unregister before the matching teardown. Patch 5 moves octeontx2 AF devlink registration after SR-IOV setup and switch lock initialization. Patch 6 moves octeontx2 PF devlink registration after PF SR-IOV state setup. Patch 7 adds the devlink_eswitch_mode= parser, documentation, registration-time default application and successful reload default application. Changelog: v1 -> v2: - Move default eswitch mode application into devlink core. The default is now applied during devlink registration and after a successful devlink reload that performed DRIVER_REINIT. - Remove the exported devl_apply_default_esw_mode() driver API and the mlx5 driver-side call to it. - Skip devlink health recovery notifications while the devlink instance is not registered, so drivers can move registration later without early health work hitting registration assertions. - Move mlx5 devlink registration after device initialization, including the lightweight init path, so the core can apply the default through the normal registration flow. - Move the matching netdevsim and mlx5 unregister paths before object teardown, so unregister notifications come from devl_unregister() and the later object teardown paths run while the devlink instance is no longer registered. - Add registration-ordering preparation patches for netdevsim and octeontx2 AF/PF, so their eswitch state is ready before registration-time defaults may call eswitch_mode_set(). [1] https://lore.kernel.org/all/20260502184153.4fd8d06f@kernel.org/ RFC V1 : https://lore.kernel.org/all/20260506123739.1959770-1-mbloch@nvidia.com/ RFC V2 : https://lore.kernel.org/all/20260510185424.2041415-1-mbloch@nvidia.com/ v1 : https://lore.kernel.org/all/20260521072434.362624-1-tariqt@nvidia.com/ Signed-off-by: Mark Bloch Mark Bloch (7): devlink: Skip health recover notifications before register netdevsim: Register devlink after device init net/mlx5: Clear FW reset-in-progress bit before reload net/mlx5: Register devlink after device init octeontx2-af: Register devlink after SR-IOV init octeontx2-pf: Register devlink after SR-IOV state init devlink: Add eswitch mode boot defaults .../admin-guide/kernel-parameters.txt | 25 ++ .../networking/devlink/devlink-defaults.rst | 80 ++++++ Documentation/networking/devlink/index.rst | 1 + .../net/ethernet/marvell/octeontx2/af/rvu.c | 24 +- .../ethernet/marvell/octeontx2/nic/otx2_pf.c | 17 +- .../ethernet/mellanox/mlx5/core/fw_reset.c | 28 +- .../net/ethernet/mellanox/mlx5/core/main.c | 34 ++- drivers/net/netdevsim/dev.c | 15 +- net/devlink/core.c | 261 ++++++++++++++++++ net/devlink/dev.c | 3 + net/devlink/devl_internal.h | 1 + net/devlink/health.c | 3 +- 12 files changed, 443 insertions(+), 49 deletions(-) create mode 100644 Documentation/networking/devlink/devlink-defaults.rst base-commit: dfcc2ff12925d99e858eaf539eaa4aaaf81fe2a6 -- 2.34.1