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Wed, 3 Jun 2026 12:33:39 -0700 From: Mark Bloch To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Jonathan Corbet , Shuah Khan , Jiri Pirko , Simon Horman , Sunil Goutham , Linu Cherian , Geetha sowjanya , hariprasad , Subbaraya Sundeep , Bharat Bhushan , Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Borislav Petkov (AMD)" , Andrew Morton , Randy Dunlap , "Peter Zijlstra (Intel)" , Thomas Gleixner , Petr Mladek , Tejun Heo , Vlastimil Babka , Feng Tang , Dave Hansen , Christian Brauner , Dapeng Mi , Kees Cook , Marco Elver , Eric Biggers , Li RongQing , "Paul E. McKenney" , "Ethan Nelson-Moore" , , , , , Shay Drori Subject: [PATCH net-next V2 4/7] net/mlx5: Register devlink after device init Date: Wed, 3 Jun 2026 22:32:56 +0300 Message-ID: <20260603193259.3412464-5-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260603193259.3412464-1-mbloch@nvidia.com> References: <20260603193259.3412464-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000066ED:EE_|BN7PPFABD533732:EE_ X-MS-Office365-Filtering-Correlation-Id: 07584d26-6f0d-47c4-e333-08dec1a714d2 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|36860700016|82310400026|6133799003|22082099003|18002099003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: ep+rkXXe/y7ee7/4zYh+NELIWmlz3ffjY6t6bzk8B59VxFu7uUmSA78tEJ7gurB3FxRRcTVYMfL/aBO14km+7IQJSnv22vcEyghxYrdDE2YHfiABSSJea98nfXdh/Uq+lzSQeyYFTcZtDO3y5EtvkEJn5Jq0wDkVF/m5sOA2JjG/YCH6NtCKAEYdJ0WW1/vmFDX9FGZ8DiDUdKok8MJgmXfxqqd4fBo6rzG+ctFiojVJh+eWlqD0ZYppIVIFT8+VRKp0NN9J/7zOkC/vLzPyoyI1iIZNtoGFQ4hEuxVB92gEugfQLL1Jx+EiOyBstIBjki4CuOiQlqWzqturgi1tRb4w6A7NchkR5P8+A7+UJLHttkvN+mPufMob7UekL5H3njqVEoG5/oPUa5cpKQkFTJ5YTAr+8M+AxDvgD6kyamOf+uBVr1Z/NUE/10b2P/YXt29Lo2+JKrGaRIichhCNu7FIrFYyLmWMO1JWQzJtxuIpgua5/qhKqV2hgeeQdPk2Tv9VmON211Bmd40j9CcAprAbti4CvyzUJihLJrk2uxanwMaxFlLFDmtr0uF1IlJELAHeP6HFxfMAVO1ZS0MFK2Bu/AIApaD19vZ7RZVpdKOnWet23MkoUH3EQgCGg4IOo4TqjHGKul5zPxrxZ3DIc5B2FpsjHsuIJN/X2YLcQPkU/0NV3VPd5wWXcPqknxqhRCu4rQfEB09AMnhsfCK14D+Hw/Lc3DMkKiZxyHerr1k= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(1800799024)(36860700016)(82310400026)(6133799003)(22082099003)(18002099003)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: BVxlnWBqlXQzMXuOS1BGEWRIMqLK9yOWFICN/HSG929bQ0fnYh+TkpQUhpXr3M3Aan+/wU6XXTtY1XVXxcyd8x7dokTDR8FFsAwmok9ZsnT7+Rh4OCM490TuqzOhZDsjWo8JP8XgWIf7vEcvJEN3uTZQQgo03OGjK9ek10rlkjNfYzREjGFU1vy393mTXitzuNDDKTpxwOTpYw0yaEgsQ6YHft6Kz6cBUadyJ3p5KOa5qN+S/L8uvwaZ9V5wAW0lZ/t36kLLusfH8vZXwHBa3xaCfTyAttzI3zGBcQRV551/8eZwDygIbCTGjKtTYzkjd+XQrLKR4MMYftq1kIypffyw5fxkkmmWiflhglv6m/6YPMT52VKGhhMx8HquQ0uxbxfhtDqNOJlVg7lDEf5VVM9QmsY/4Fd180IROH7seygjdmRB7vfw7nF43UsWN5rd X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jun 2026 19:34:08.5582 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 07584d26-6f0d-47c4-e333-08dec1a714d2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000066ED.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPFABD533732 devl_register() makes the devlink instance visible to userspace. A later patch also makes registration the point where devlink core may call eswitch_mode_set() to apply a boot-time default eswitch mode. Move mlx5 devlink registration after mlx5 device initialization completes, including the lightweight init path, so registration-time devlink operations see initialized driver state. Move devl_unregister() before the matching teardown paths, so unregister notifications are emitted from devl_unregister() before mlx5 removes the devlink objects. Add a devl-locked uninit helper so failed nested devlink setup can unwind the initialized device before the instance is registered. Reviewed-by: Shay Drori Signed-off-by: Mark Bloch --- .../net/ethernet/mellanox/mlx5/core/main.c | 34 ++++++++++++++----- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c index 0c6e4efe38c8..ab3d3ff10f1a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -1455,31 +1455,40 @@ int mlx5_init_one_devl_locked(struct mlx5_core_dev *dev) return err; } +static void mlx5_uninit_one_devl_locked(struct mlx5_core_dev *dev); + int mlx5_init_one(struct mlx5_core_dev *dev) { struct devlink *devlink = priv_to_devlink(dev); int err; devl_lock(devlink); + err = mlx5_init_one_devl_locked(dev); + if (err) + goto unlock; + if (dev->shd) { err = devl_nested_devlink_set(dev->shd, devlink); if (err) - goto unlock; + goto err_uninit; } + devl_register(devlink); - err = mlx5_init_one_devl_locked(dev); - if (err) - devl_unregister(devlink); + devl_unlock(devlink); + return 0; + +err_uninit: + mlx5_uninit_one_devl_locked(dev); unlock: devl_unlock(devlink); return err; } -void mlx5_uninit_one(struct mlx5_core_dev *dev) +static void mlx5_uninit_one_devl_locked(struct mlx5_core_dev *dev) { struct devlink *devlink = priv_to_devlink(dev); - devl_lock(devlink); + devl_assert_locked(devlink); mutex_lock(&dev->intf_state_mutex); mlx5_hwmon_dev_unregister(dev); @@ -1501,7 +1510,15 @@ void mlx5_uninit_one(struct mlx5_core_dev *dev) mlx5_function_teardown(dev, true); out: mutex_unlock(&dev->intf_state_mutex); +} + +void mlx5_uninit_one(struct mlx5_core_dev *dev) +{ + struct devlink *devlink = priv_to_devlink(dev); + + devl_lock(devlink); devl_unregister(devlink); + mlx5_uninit_one_devl_locked(dev); devl_unlock(devlink); } @@ -1635,7 +1652,6 @@ int mlx5_init_one_light(struct mlx5_core_dev *dev) int err; devl_lock(devlink); - devl_register(devlink); dev->state = MLX5_DEVICE_STATE_UP; err = mlx5_function_enable(dev, true, mlx5_tout_ms(dev, FW_PRE_INIT_TIMEOUT)); if (err) { @@ -1655,6 +1671,7 @@ int mlx5_init_one_light(struct mlx5_core_dev *dev) goto query_hca_caps_err; } + devl_register(devlink); devl_unlock(devlink); return 0; @@ -1662,7 +1679,6 @@ int mlx5_init_one_light(struct mlx5_core_dev *dev) mlx5_function_disable(dev, true); out: dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR; - devl_unregister(devlink); devl_unlock(devlink); return err; } @@ -1672,8 +1688,8 @@ void mlx5_uninit_one_light(struct mlx5_core_dev *dev) struct devlink *devlink = priv_to_devlink(dev); devl_lock(devlink); - mlx5_devlink_params_unregister(priv_to_devlink(dev)); devl_unregister(devlink); + mlx5_devlink_params_unregister(priv_to_devlink(dev)); devl_unlock(devlink); if (dev->state != MLX5_DEVICE_STATE_UP) return; -- 2.34.1