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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Dragos Tatulea , Cosmin Ratiu , Nathan Chancellor , Raed Salem , linux-kernel@vger.kernel.org (open list) Subject: [PATCH rdma-next 05/15] mlx5: Rename IFC bits of relaxed ordering fields Date: Sun, 26 Jul 2026 12:29:19 +0300 Message-ID: <20260726092943.2880176-6-michaelgur@nvidia.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260726092943.2880176-1-michaelgur@nvidia.com> References: <20260726092943.2880176-1-michaelgur@nvidia.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: FR0P281CA0138.DEUP281.PROD.OUTLOOK.COM (2603:10a6:d10:96::7) To LV8PR12MB9715.namprd12.prod.outlook.com (2603:10b6:408:2a0::7) Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV8PR12MB9715:EE_|CY8PR12MB7611:EE_ X-MS-Office365-Filtering-Correlation-Id: 2cb6b3b8-cb9d-4415-d3a3-08deeaf88be7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|23010399003|366016|1800799024|10067099003|18002099003|22082099003|56012099006|11063799006; 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Reviewed-by: Yishai Hadas Signed-off-by: Michael Gur --- drivers/infiniband/hw/mlx5/main.c | 8 ++++---- drivers/infiniband/hw/mlx5/mr.c | 16 ++++++++-------- drivers/infiniband/hw/mlx5/umr.c | 14 +++++++------- drivers/infiniband/hw/mlx5/umr.h | 8 ++++---- .../net/ethernet/mellanox/mlx5/core/en/params.c | 2 +- .../net/ethernet/mellanox/mlx5/core/en_common.c | 8 ++++---- include/linux/mlx5/mlx5_ifc.h | 12 ++++++------ 7 files changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c index d65ebdef2823..2f16fa40d269 100644 --- a/drivers/infiniband/hw/mlx5/main.c +++ b/drivers/infiniband/hw/mlx5/main.c @@ -3513,13 +3513,13 @@ mlx5_ib_create_data_direct_resources(struct mlx5_ib_dev *dev) dev->ddr.pdn = pdn; /* create another mkey with RO support */ - if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write)) { - MLX5_SET(mkc, mkc, relaxed_ordering_write, 1); + if (MLX5_CAP_GEN(dev->mdev, mkc_order_write_after_write_ro)) { + MLX5_SET(mkc, mkc, order_write_after_write, 1); ro_supp = true; } - if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read)) { - MLX5_SET(mkc, mkc, relaxed_ordering_read, 1); + if (MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read)) { + MLX5_SET(mkc, mkc, pci_relaxed_ordered_read, 1); ro_supp = true; } diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c index 00e13028762a..53bc844a7fc8 100644 --- a/drivers/infiniband/hw/mlx5/mr.c +++ b/drivers/infiniband/hw/mlx5/mr.c @@ -72,14 +72,14 @@ static void set_mkc_access_pd_addr_fields(void *mkc, int acc, u64 start_addr, MLX5_SET(mkc, mkc, lr, 1); if (acc & IB_ACCESS_RELAXED_ORDERING) { - if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write)) - MLX5_SET(mkc, mkc, relaxed_ordering_write, 1); + if (MLX5_CAP_GEN(dev->mdev, mkc_order_write_after_write_ro)) + MLX5_SET(mkc, mkc, order_write_after_write, 1); - if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) || + if (MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read) || (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_pci_enabled) && pcie_relaxed_ordering_enabled(dev->mdev->pdev))) - MLX5_SET(mkc, mkc, relaxed_ordering_read, 1); + MLX5_SET(mkc, mkc, pci_relaxed_ordered_read, 1); } MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn); @@ -147,14 +147,14 @@ static int get_unchangeable_access_flags(struct mlx5_ib_dev *dev, ret |= IB_ACCESS_REMOTE_ATOMIC; if ((access_flags & IB_ACCESS_RELAXED_ORDERING) && - MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) && - !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)) + MLX5_CAP_GEN(dev->mdev, mkc_order_write_after_write_ro) && + !MLX5_CAP_GEN(dev->mdev, order_write_after_write_umr)) ret |= IB_ACCESS_RELAXED_ORDERING; if ((access_flags & IB_ACCESS_RELAXED_ORDERING) && - (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) || + (MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read) || MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_pci_enabled)) && - !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)) + !MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read_umr)) ret |= IB_ACCESS_RELAXED_ORDERING; return ret; diff --git a/drivers/infiniband/hw/mlx5/umr.c b/drivers/infiniband/hw/mlx5/umr.c index 80d0d190b26c..05ab0a32ded6 100644 --- a/drivers/infiniband/hw/mlx5/umr.c +++ b/drivers/infiniband/hw/mlx5/umr.c @@ -59,10 +59,10 @@ static __be64 get_umr_update_access_mask(struct mlx5_ib_dev *dev) if (MLX5_CAP_GEN(dev->mdev, atomic)) result |= MLX5_MKEY_MASK_A; - if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)) + if (MLX5_CAP_GEN(dev->mdev, order_write_after_write_umr)) result |= MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE; - if (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)) + if (MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read_umr)) result |= MLX5_MKEY_MASK_RELAXED_ORDERING_READ; return cpu_to_be64(result); @@ -88,11 +88,11 @@ static int umr_check_mkey_mask(struct mlx5_ib_dev *dev, u64 mask) return -EPERM; if (mask & MLX5_MKEY_MASK_RELAXED_ORDERING_WRITE && - !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)) + !MLX5_CAP_GEN(dev->mdev, order_write_after_write_umr)) return -EPERM; if (mask & MLX5_MKEY_MASK_RELAXED_ORDERING_READ && - !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)) + !MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read_umr)) return -EPERM; return 0; @@ -446,7 +446,7 @@ static void mlx5r_umr_set_access_flags(struct mlx5_ib_dev *dev, unsigned int access_flags) { bool ro_read = (access_flags & IB_ACCESS_RELAXED_ORDERING) && - (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) || + (MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read) || pcie_relaxed_ordering_enabled(dev->mdev->pdev)); MLX5_SET(mkc, seg, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC)); @@ -454,9 +454,9 @@ static void mlx5r_umr_set_access_flags(struct mlx5_ib_dev *dev, MLX5_SET(mkc, seg, rr, !!(access_flags & IB_ACCESS_REMOTE_READ)); MLX5_SET(mkc, seg, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE)); MLX5_SET(mkc, seg, lr, 1); - MLX5_SET(mkc, seg, relaxed_ordering_write, + MLX5_SET(mkc, seg, order_write_after_write, !!(access_flags & IB_ACCESS_RELAXED_ORDERING)); - MLX5_SET(mkc, seg, relaxed_ordering_read, ro_read); + MLX5_SET(mkc, seg, pci_relaxed_ordered_read, ro_read); } int mlx5r_umr_rereg_pd_access(struct mlx5_ib_mr *mr, struct ib_pd *pd, diff --git a/drivers/infiniband/hw/mlx5/umr.h b/drivers/infiniband/hw/mlx5/umr.h index bda7123781a9..04dec726b267 100644 --- a/drivers/infiniband/hw/mlx5/umr.h +++ b/drivers/infiniband/hw/mlx5/umr.h @@ -61,14 +61,14 @@ static inline bool mlx5r_umr_can_reconfig(struct mlx5_ib_dev *dev, return false; if ((diffs & IB_ACCESS_RELAXED_ORDERING) && - MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) && - !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)) + MLX5_CAP_GEN(dev->mdev, mkc_order_write_after_write_ro) && + !MLX5_CAP_GEN(dev->mdev, order_write_after_write_umr)) return false; if ((diffs & IB_ACCESS_RELAXED_ORDERING) && - (MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) || + (MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read) || MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_pci_enabled)) && - !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)) + !MLX5_CAP_GEN(dev->mdev, pci_relaxed_ordered_read_umr)) return false; return true; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c index 1f4a547917ba..a52ff01038e2 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c @@ -912,7 +912,7 @@ static void mlx5e_build_rx_cq_param(struct mlx5_core_dev *mdev, static u8 rq_end_pad_mode(struct mlx5_core_dev *mdev, struct mlx5e_params *params) { bool lro_en = params->packet_merge.type == MLX5E_PACKET_MERGE_LRO; - bool ro = MLX5_CAP_GEN(mdev, relaxed_ordering_write); + bool ro = MLX5_CAP_GEN(mdev, mkc_order_write_after_write_ro); return ro && lro_en ? MLX5_WQ_END_PAD_MODE_NONE : MLX5_WQ_END_PAD_MODE_ALIGN; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c index c2d4bae533de..2dbcf6673916 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_common.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_common.c @@ -40,13 +40,13 @@ void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc) { - bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write); - bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read) || + bool ro_write = MLX5_CAP_GEN(mdev, mkc_order_write_after_write_ro); + bool ro_read = MLX5_CAP_GEN(mdev, pci_relaxed_ordered_read) || (pcie_relaxed_ordering_enabled(mdev->pdev) && MLX5_CAP_GEN(mdev, relaxed_ordering_read_pci_enabled)); - MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_read); - MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_write); + MLX5_SET(mkc, mkc, pci_relaxed_ordered_read, ro_read); + MLX5_SET(mkc, mkc, order_write_after_write, ro_write); } int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn, u32 *mkey) diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h index 695c86ee6d7a..0593913fd25f 100644 --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h @@ -1709,15 +1709,15 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 max_sgl_for_optimized_performance[0x8]; u8 log_max_cq_sz[0x8]; - u8 relaxed_ordering_write_umr[0x1]; - u8 relaxed_ordering_read_umr[0x1]; + u8 order_write_after_write_umr[0x1]; + u8 pci_relaxed_ordered_read_umr[0x1]; u8 reserved_at_d2[0x7]; u8 virtio_net_device_emualtion_manager[0x1]; u8 virtio_blk_device_emualtion_manager[0x1]; u8 log_max_cq[0x5]; u8 log_max_eq_sz[0x8]; - u8 relaxed_ordering_write[0x1]; + u8 mkc_order_write_after_write_ro[0x1]; u8 relaxed_ordering_read_pci_enabled[0x1]; u8 log_max_mkey[0x6]; u8 reserved_at_f0[0x6]; @@ -1949,7 +1949,7 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_320[0x3]; u8 log_max_transport_domain[0x5]; u8 reserved_at_328[0x2]; - u8 relaxed_ordering_read[0x1]; + u8 pci_relaxed_ordered_read[0x1]; u8 log_max_pd[0x5]; u8 dp_ordering_ooo_all_ud[0x1]; u8 dp_ordering_ooo_all_uc[0x1]; @@ -4524,7 +4524,7 @@ struct mlx5_ifc_mkc_bits { u8 reserved_at_2[0x1]; u8 access_mode_4_2[0x3]; u8 reserved_at_6[0x7]; - u8 relaxed_ordering_write[0x1]; + u8 order_write_after_write[0x1]; u8 reserved_at_e[0x1]; u8 small_fence_on_rdma_read_response[0x1]; u8 umr_en[0x1]; @@ -4566,7 +4566,7 @@ struct mlx5_ifc_mkc_bits { u8 translations_octword_size[0x20]; u8 reserved_at_1c0[0x19]; - u8 relaxed_ordering_read[0x1]; + u8 pci_relaxed_ordered_read[0x1]; u8 log_page_size[0x6]; u8 reserved_at_1e0[0x5]; -- 2.52.0