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Tue, 8 Sep 2026 08:30:16 -0700 From: Yishai Hadas To: , CC: , , , , , , , , , , , , , , , Subject: [PATCH rdma-next 10/15] RDMA/mlx5: Set WQ event handler before firmware RQ insertion Date: Tue, 8 Sep 2026 18:28:46 +0300 Message-ID: <20260908152851.1307294-11-yishaih@nvidia.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20260908152851.1307294-1-yishaih@nvidia.com> References: <20260908152851.1307294-1-yishaih@nvidia.com> Precedence: bulk X-Mailing-List: linux-rdma@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF000000A0:EE_|IA1PR12MB7711:EE_ X-MS-Office365-Filtering-Correlation-Id: 5d410dd4-cbf5-4d21-d20c-08df0dbe2a54 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700016|7416014|376014|23010399003|10067099003|11063799006|56012099006|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: CkFzyO301M23prhBzELxrjCm7eG9b8M2gqKWqJBWGUq/0Ev+eYW1GmHP2VCffECTDOO/vjoulS/9thbuV30L0zNOjHXsjxAeZBcZAb8wPgGBrOOorDwqJmgjk1eGuwiwTKQiCE9+SKMdqLQjFbYmBZ2bm/uiXlEZWghh6u6JwlXyDnC1WZul/YtCIWvEutYvMmdy+w9ujc1sVDwHQM/vxSZfQ0/uEdIorJnP3J2XK/0gYwhtbr9ZOyJ6eJst0iSP3VogRaCQRghwEMOkOODethNZCax7PVhZHpxOkBF9QIB5PdPWxooajePt7CxVbXVx/9f+EXzu1Bbz8PjaCsWJgGTKyw+mPgvq14+i8NPKOs4ZQS01S7egeotFmWfizrqoBsb8pG2V74sWtNvARwopuRvLLxVmfmaoZvcFoyUHF4kjUXbMjyqmWkqzdC3Eb/1b X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2026 15:30:51.3683 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d410dd4-cbf5-4d21-d20c-08df0dbe2a54 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF000000A0.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7711 mlx5_ib_create_wq() calls create_rq(), which inserts the RQ's mlx5_core_qp into dev->qp_table.tree via mlx5_core_create_rq_tracked() -> create_resource_common(), making it immediately visible to rsc_event_notifier(). rwq->core_qp.event was assigned only after create_rq() returned, and after several more steps (wq_num/state setup, ib_respond_udata()), leaving a wide window where a firmware WQ_CATAS_ERROR EQE would find rwq->core_qp.event still NULL and hit the WARN_ON_ONCE(!qp->event) guard in rsc_event_notifier(), dropping the event instead of delivering it. Move the assignment right after the mlx5_ib_rwq allocation, before create_rq() is called. mlx5_ib_wq_event() already null-checks rwq->ibwq.event_handler before touching it, so setting core_qp.event early is safe even though ibwq.event_handler is still assigned later. Fixes: 350d0e4c7e4b ("IB/mlx5: Track asynchronous events on a receive work queue") Signed-off-by: Yishai Hadas --- drivers/infiniband/hw/mlx5/qp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c index d4d439ebb595..d8e8a84ff3f1 100644 --- a/drivers/infiniband/hw/mlx5/qp.c +++ b/drivers/infiniband/hw/mlx5/qp.c @@ -5618,6 +5618,7 @@ struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, rwq = kzalloc_obj(*rwq); if (!rwq) return ERR_PTR(-ENOMEM); + rwq->core_qp.event = mlx5_ib_wq_event; err = prepare_user_rq(pd, init_attr, udata, rwq); if (err) goto err; @@ -5641,7 +5642,6 @@ struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, goto err_copy; } - rwq->core_qp.event = mlx5_ib_wq_event; rwq->ibwq.event_handler = init_attr->event_handler; return &rwq->ibwq; -- 2.18.1