Linux RDMA and InfiniBand development
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From: Leon Romanovsky <leon@kernel.org>
To: Yishai Hadas <yishaih@nvidia.com>
Cc: jgg@ziepe.ca, linux-rdma@vger.kernel.org,
	selvin.xavier@broadcom.com, kalesh-anakkur.purayil@broadcom.com,
	chengyou@linux.alibaba.com, kaishen@linux.alibaba.com,
	tangchengchang@huawei.com, huangjunxian6@hisilicon.com,
	abhijit.gangurde@amd.com, allen.hubbe@amd.com,
	longli@microsoft.com, kotaranov@microsoft.com,
	mkalderon@marvell.com, bryan-bt.tan@broadcom.com,
	vishnu.dasa@broadcom.com, maorg@nvidia.com
Subject: Re: [PATCH rdma-next 07/15] RDMA/umem: Derive DMA direction from IB access flags
Date: Tue, 15 Sep 2026 10:35:45 +0300	[thread overview]
Message-ID: <20260915073545.GE13683@unreal> (raw)
In-Reply-To: <20260908152851.1307294-8-yishaih@nvidia.com>

On Tue, Sep 08, 2026 at 06:28:43PM +0300, Yishai Hadas wrote:
> ib_umem_get_desc() / ib_umem_get_attr() / ib_umem_get_attr_or_va() can
> now derive the DMA direction from the IB access flags instead of always
> mapping DMA_BIDIRECTIONAL:
> 
>   - No write access granted (as determined by ib_access_writable():
>     IB_ACCESS_LOCAL_WRITE, IB_ACCESS_REMOTE_WRITE,
>     IB_ACCESS_REMOTE_ATOMIC, or IB_ACCESS_MW_BIND): the NIC may only
>     read the pages, so DMA_TO_DEVICE. This covers all callers that
>     pass access=0 (SRQ WQE rings, QP SQ/RQ WQE rings, doorbell
>     records) and MRs registered without write access
>     (IB_ACCESS_REMOTE_READ only).
> 
>   - Any such flag set: DMA_BIDIRECTIONAL, unchanged behaviour.
> 
> This is not just a theoretical default: it has been verified, driver by
> driver, against every QP SQ/RQ, SRQ, and doorbell-record buffer in the
> tree pinned this way -- mlx5, mlx4, bnxt_re, efa, ionic, qedr, mana,
> erdma, hns, and irdma all externalize their producer/consumer
> bookkeeping through a separate doorbell/UAR MMIO write or a distinct
> completion queue, never by the device writing back into the same buffer
> the CPU posts WQEs into. vmw_pvrdma is the sole exception, already
> pinning its QP/SRQ rings with IB_ACCESS_LOCAL_WRITE (see the earlier
> fix), so it continues to correctly derive DMA_BIDIRECTIONAL here without
> any special-casing.

Please read commit messages and remove the AI slop above. It is part of
claude/codex/... Intermediate prose which shouldn't be in the commit
message.

> 
> For dmabuf buffers the direction is managed by the dmabuf subsystem and
> ib_umem_get_desc() routes them unchanged, ignoring the derived
> direction. CQ buffers already get their own tighter, unconditional
> DMA_FROM_DEVICE mapping from the previous patch and are unaffected by
> this rule.

Same.

> 
> Security gain by platform:
>   - Platforms with a write-enforcing IOMMU (e.g. CoCo guests backed by
>     ARM SMMU or Intel VT-d in strict mode): a hostile device is
>     hardware-prevented from writing to read-only buffers (WQEs,
>     doorbell records), limiting corruption.
>   - Standard deployments without IOMMU direction enforcement: no
>     practical security effect today, but the correct semantic
>     declaration and zero runtime cost.
> 
> Signed-off-by: Yishai Hadas <yishaih@nvidia.com>
> ---
>  drivers/infiniband/core/umem.c | 23 ++++++++++++++++++++---
>  1 file changed, 20 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/infiniband/core/umem.c b/drivers/infiniband/core/umem.c
> index f1da70c4e352..490ce660193e 100644
> --- a/drivers/infiniband/core/umem.c
> +++ b/drivers/infiniband/core/umem.c
> @@ -329,7 +329,20 @@ struct ib_umem *ib_umem_get_desc(struct ib_device *device,
>  				 const struct ib_uverbs_buffer_desc *desc,
>  				 int access)
>  {
> -	return __ib_umem_get_desc_dir(device, desc, access, DMA_BIDIRECTIONAL);
> +	/*
> +	 * Derive the DMA direction from the IB access flags.  If the caller
> +	 * grants no write access (local or remote), the NIC may only read the
> +	 * pages - use DMA_TO_DEVICE so that platforms with a write-enforcing
> +	 * IOMMU (e.g. CoCo / SMMU with SMMU_CB_ARC_FAULT_ENABLE) can enforce
> +	 * the restriction.
> +	 *
> +	 * Where the IOMMU does not enforce direction (most x86 bare-metal
> +	 * deployments today) this has no security effect, but is still the
> +	 * correct semantic declaration and costs nothing.
> +	 */

Please remove these useless comments.

> +	return __ib_umem_get_desc_dir(device, desc, access,
> +				      ib_access_writable(access) ?
> +				      DMA_BIDIRECTIONAL : DMA_TO_DEVICE);

Write some simple wrapper for this pattern.

Thanks

  reply	other threads:[~2026-09-15  7:35 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-08 15:28 [PATCH rdma-next 00/15] DMA direction and mlx5 driver correctness fixes Yishai Hadas
2026-09-08 15:28 ` [PATCH rdma-next 01/15] RDMA/erdma: Pin CQ buffer writable to match device DMA write access Yishai Hadas
2026-09-08 15:28 ` [PATCH rdma-next 02/15] RDMA/hns: " Yishai Hadas
2026-09-08 15:28 ` [PATCH rdma-next 03/15] RDMA/vmw_pvrdma: Pin QP and SRQ rings " Yishai Hadas
2026-09-08 15:28 ` [PATCH rdma-next 04/15] RDMA/umem: Reuse ib_umem_get_cq_buf_or_va() for VA-only CQ pinning Yishai Hadas
2026-09-08 15:28 ` [PATCH rdma-next 05/15] RDMA/umem: Support an explicit DMA direction other than DMA_BIDIRECTIONAL Yishai Hadas
2026-09-08 15:28 ` [PATCH rdma-next 06/15] RDMA/umem: Map CQ buffers DMA_FROM_DEVICE Yishai Hadas
2026-09-08 15:28 ` [PATCH rdma-next 07/15] RDMA/umem: Derive DMA direction from IB access flags Yishai Hadas
2026-09-15  7:35   ` Leon Romanovsky [this message]
2026-09-08 15:28 ` [PATCH rdma-next 08/15] RDMA/mlx5: Fix mlx5_ib_dev_res_init() failure when XRC cap is absent Yishai Hadas
2026-09-08 15:28 ` [PATCH rdma-next 09/15] RDMA/mlx5: Put resource reference in mlx5_ib_wq_event() Yishai Hadas
2026-09-08 15:28 ` [PATCH rdma-next 10/15] RDMA/mlx5: Set WQ event handler before firmware RQ insertion Yishai Hadas
2026-09-08 15:28 ` [PATCH rdma-next 11/15] RDMA/mlx5: Set SRQ event handler before xarray insertion Yishai Hadas
2026-09-08 15:28 ` [PATCH rdma-next 12/15] RDMA/mlx5: Set RQ event handler for raw-packet QP Yishai Hadas
2026-09-08 15:28 ` [PATCH rdma-next 13/15] RDMA/mlx5: Set QP event handler before firmware QPC insertion Yishai Hadas
2026-09-08 15:28 ` [PATCH rdma-next 14/15] RDMA/mlx5: Initialize QP/RQ/SQ resource refcount before publishing it Yishai Hadas
2026-09-08 15:28 ` [PATCH rdma-next 15/15] RDMA/mlx5: Fix signed integer overflow in EQE qp_srq type shift Yishai Hadas
2026-09-15  7:37 ` [PATCH rdma-next 00/15] DMA direction and mlx5 driver correctness fixes Leon Romanovsky

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