From: Yevgeny Kliteynik <kliteyn@nvidia.com>
To: Dan Carpenter <dan.carpenter@oracle.com>
Cc: <linux-rdma@vger.kernel.org>
Subject: Re: [bug report] net/mlx5: DR, Add STEv1 setters and getters
Date: Sat, 6 Feb 2021 22:20:55 +0200 [thread overview]
Message-ID: <35cbffa9-58bc-c2be-2ec7-12339d12547e@nvidia.com> (raw)
In-Reply-To: <YB1B/iHMlHHnOWCh@mwanda>
On 05-Feb-21 15:02, Dan Carpenter wrote:
>
> Hello Yevgeny Kliteynik,
>
> The patch a6098129c781: "net/mlx5: DR, Add STEv1 setters and getters"
> from Sep 22, 2020, leads to the following static checker warning:
>
> drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c:268 dr_ste_v1_get_miss_addr()
> warn: potential shift truncation. '0xff (0-255) << 26'
>
> drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c
> 264 static u64 dr_ste_v1_get_miss_addr(u8 *hw_ste_p)
> 265 {
> 266 u64 index =
> 267 (MLX5_GET(ste_match_bwc_v1, hw_ste_p, miss_address_31_6) |
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> 268 MLX5_GET(ste_match_bwc_v1, hw_ste_p, miss_address_39_32) << 26);
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>
> index is a u64 but the right side is a two u32s. The << 26 can shift
> wrap potentially according to Smatch.
Thanks Dan, will send a fix shortly.
-- YK
> 269
> 270 return index << 6;
> 271 }
>
> regards,
> dan carpenter
>
prev parent reply other threads:[~2021-02-06 20:21 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-05 13:02 [bug report] net/mlx5: DR, Add STEv1 setters and getters Dan Carpenter
2021-02-06 20:20 ` Yevgeny Kliteynik [this message]
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