Re: strong ordering for data registered memory

[Caitlin Bestler <cait-DpaxOq6QOWMAvxtiuMwx3w@public.gmane.org>]

>On Thu Nov 12 12:43 , David Brean <David.Brean-UdXhSnd/wVw@public.gmane.org> wrote:See section 4 in the paper called "High Performance RDMA Based MPI Implementation over InfiniBand" on the MVAPICH web page for description of one implementation that polls on data buffers.  Specifically, look at text around the statement "Although the approach uses the in-order implementation of hardware for RDMA write which is not specified in the InfiniBand standard, this feature is very likely to be kept by different hardware designers."  Although this paper is describing a PCI-X implementation, the feature is also exists on PCIe.
>
>It's assumed that the host memory interconnect complies with statements described in the "Update Ordering and Granularity Provided by a Write Transaction" of the PCI spec.  This particular application depends on PCI WRITE behavior, not READ.
>
>Does this help?
>

A simplified way of looking at this requirement is that the last N bytes of the RDMA Write payload require the same ordering guarantees as a CQE would have had.

This is of course ironic since the technique was developed to avoid the overhead of the CQ.

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