Re: [PATCH for-3.11 7/7] IB/iser: Introduce fast memory registration model (FRWR)

[Bart Van Assche <bvanassche-HInyCGIudOg@public.gmane.org>]

On 07/24/13 18:28, Or Gerlitz wrote:
> On 23/07/2013 17:47, Bart Van Assche wrote:
>> Still regarding page sizes: shouldn't ib_alloc_fast_reg_page_list()
>> and ib_alloc_fast_reg_mr() multiply the SG list length by PAGE_SIZE /
>> SIZE_4K to compensate for page size differences on architectures where
>> virtual memory pages are larger than 4KB ?
>
> My understanding of the API is that it assumes that the HW is capable to
> change the page shift (size) associated with certain fast_reg MR for
> each mapping.

I think you have a point here. Although I'm not sure this is what you 
had in mind, using PAGE_SIZE / PAGE_SHIFT instead of SIZE_4K / SHIFT_4K 
should work better on architectures with a page size larger than 4KB. On 
mlx4 the largest supported page list length is 511 
(MLX4_MAX_FAST_REG_PAGES). So the former option should allow to support 
larger sg lists on such architectures (up to length 511) compared to the 
latter (up to length 511/(64/4) = 31 for 64KB pages).

Bart.
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