Re: [PATCH 04/15] yunsilicon: add event queues, interrupts and the

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 8 potential issue(s) to consider:
- [High] net: xsc: bitwise XOR logic error in next_eqe_sw() halts event queue processing
- [High] net: xsc: skipping teardown when firmware is offline causes Use-After-Free and resource leaks
- [High] net: xsc: spoofing device->numa_node during DMA allocation causes data races
- [High] yunsilicon: vmap() on dma_alloc_coherent() memory creates illegal cache aliases
- [Medium] net: xsc: multiple memory leaks and incorrect affinity setup in cpumask management
- [Medium] net: xsc: vunmap skipped on 32-bit architectures causes vmalloc memory leak
- [Medium] net: xsc: data race on link_event_handler can lead to NULL pointer dereference
- [Medium] net: xsc: xsc_core_vector2eqn leaves irqn uninitialized when MSI-X is disabled
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[Severity: High]
File: ..., Function: ..., Line: ...
Your question here...

Do not use '> diff' or any direct source recitation. Respond only with the prose descriptions.commit a872f21fb08a814fac5b1a6b91049b643f0a1ed7
Author: Xin Tian <tianx@yunsilicon.com>

yunsilicon: add event queues, interrupts and the auxiliary bus

This commit adds event queues, MSI-X vector handling, and auxiliary bus
glue for the yunsilicon driver. It sets up the PCI core to request vectors,
create completion queues, and publish auxiliary devices for the ethernet and
RDMA drivers.

[Severity: High]
In drivers/net/ethernet/yunsilicon/xsc/pci/eq.c, within the next_eqe_sw()
function, the logic for advancing the consumer index performs a bitwise XOR
against !!(eq->cons_index & eq->nent) with (eqe->owner_data & XSC_EQE_OWNER).
Because XSC_EQE_OWNER is BIT(7) (128), when the hardware sets the owner bit,
this evaluates to 128 ^ 1, which equals 129. Since 129 is non-zero, it returns
NULL instead of the event queue entry. Will this cause the event queue to halt
completely after exactly one cycle? Would it be better to normalize the left
side to a boolean first?

[Severity: High]
In drivers/net/ethernet/yunsilicon/xsc/pci/eq.c, within xsc_destroy_unmap_eq(),
and in drivers/net/ethernet/yunsilicon/xsc/pci/pci_irq.c within both
xsc_free_irq_vectors() and xsc_free_irq(), the functions check if the firmware
is available and return early if it is not. By returning early, critical
cleanup operations like free_irq(), pci_free_irq_vectors(), and
xsc_buf_free() are skipped. Does skipping free_irq() leave the interrupt
handler active to dereference the subsequently freed `eq` object, causing a
Use-After-Free? Will this also leak PCI MSI-X allocations?

[Severity: Medium]
In drivers/net/ethernet/yunsilicon/xsc/pci/pci_irq.c, the function
set_comp_irq_affinity_hint() is called in a loop over the number of vectors.
Inside this loop, it unconditionally allocates xdev->xps_cpumask using
zalloc_cpumask_var(). Does this repeatedly overwrite the pointer and
permanently leak memory on every iteration when CONFIG_CPUMASK_OFFSTACK=y?
Additionally, if the allocation fails, it returns without freeing eq->mask.
Also, when setting the affinity hint, the code passes the newly allocated
and empty eq->mask to irq_set_affinity_hint() instead of the populated
xdev->xps_cpumask. Finally, if xsc_cmd_enable_msix() fails in
xsc_irq_eq_create(), the error path jumps to err_free_irq_evnt, which skips
clear_comp_irq_affinity_hints(). Will this leak all successfully allocated
cpumasks?

[Severity: Medium]
In drivers/net/ethernet/yunsilicon/xsc/pci/alloc.c, within xsc_buf_free(),
there is a check that only calls vunmap() if BITS_PER_LONG == 64. However, in
xsc_buf_alloc(), the memory is unconditionally mapped using vmap() when the
requested size exceeds the direct mapping threshold. Will guarding the vunmap()
with an architecture check permanently leak the mapping on 32-bit platforms
every time a multi-page buffer is freed?

[Severity: Medium]
In drivers/net/ethernet/yunsilicon/xsc/pci/pci_irq.c, within xsc_event_work(),
the link event handler is checked for NULL before being called. However,
xsc_irq_event_unregister() can concurrently set xdev->link_event_handler to
NULL. Can the compiler issue two separate memory loads for the check and the
call, leading to a NULL pointer dereference if the pointer is cleared between
the two operations? Should this use READ_ONCE() to load the pointer into a
local variable first?

[Severity: High]
In drivers/net/ethernet/yunsilicon/xsc/pci/alloc.c, the function
xsc_dma_zalloc_coherent_node() calls set_dev_node() to temporarily modify
the global device->numa_node field in order to force node-local DMA
allocations. While this is protected locally by dev_res->alloc_mutex, other
subsystems might call dev_to_node() concurrently. Can this data race cause
other parallel threads to read the spoofed value and allocate memory on the
wrong physical NUMA node?

[Severity: Medium]
In drivers/net/ethernet/yunsilicon/xsc/pci/pci_irq.c, the function
xsc_core_vector2eqn() returns 0 (success) early if xdev->caps.msix_enable is
false, without initializing the *irqn parameter. The caller, xsc_vector2eqn(),
passes this success along, which could lead to undefined behavior when it
uses the uninitialized local variable. Should *irqn be initialized before
returning on this path?

[Severity: High]
In drivers/net/ethernet/yunsilicon/xsc/pci/alloc.c, within xsc_buf_alloc(),
memory allocated via dma_alloc_coherent() is converted to struct page pointers
using virt_to_page() or vmalloc_to_page(), and then remapped contiguously
using vmap(..., PAGE_KERNEL). Because DMA coherent memory is not guaranteed
to be backed by standard linear map pages, and applying PAGE_KERNEL to
potentially uncached or write-combined memory creates conflicting cache
aliases, is this architecturally illegal? Does this bypass DMA API safety
constraints and risk memory corruption or kernel panics?

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Sashiko AI review · https://sashiko.dev/#/patchset/20261012114352.2471317-1-tianx@yunsilicon.com?part=4