Re: [PATCH v1 02/15] net/xsc: add PCI core driver skeleton

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] net/xsc: endian-dependent bitfields in struct xsc_query_vport_state_out
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commit b11d75eddf1256b25caffaed37629ef47a9f6953
Author: Xin Tian <tianx@yunsilicon.com>

net/xsc: add PCI core driver skeleton

This commit adds the PCI core driver skeleton and common firmware interface
headers for Yunsilicon XSC controllers. It implements basic PCI device
probing, BAR mapping, DMA configuration, and core device resource allocation.

> diff --git a/drivers/net/ethernet/yunsilicon/xsc/common/xsc_cmd.h b/drivers/net/ethernet/yunsilicon/xsc/common/xsc_cmd.h
> new file mode 100644
> index 0000000000000..70dbf9782f318
> --- /dev/null
> +++ b/drivers/net/ethernet/yunsilicon/xsc/common/xsc_cmd.h
[ ... ]
> +struct xsc_query_vport_state_out {
> +	struct xsc_outbox_hdr	hdr;
> +	u8			admin_state:4;
> +	u8			state:4;
> +};
> +
> +struct xsc_query_vport_state_in {
> +	struct xsc_inbox_hdr	hdr;
> +	__be32			data0;
> +#define XSC_QUERY_VPORT_OTHER_VPORT	BIT(0)
> +#define XSC_QUERY_VPORT_VPORT_NUM_MASK	GENMASK(16, 1)
> +};

[Severity: Medium]
In struct xsc_query_vport_state_out, admin_state and state are defined as
unguarded 4-bit C bitfields within a byte populated directly from the
firmware DMA response mailbox via xsc_core_query_vport_state() ->
xsc_cmd_exec() -> xsc_copy_from_rsp_msg().

On big-endian architectures, the compiler reverses the bit order of these
two 4-bit fields relative to little-endian architectures. When
xsc_core_query_vport_state() reads out.state, won't it read the admin_state
nibble instead of the operational vport state nibble on big-endian hosts?

Should struct xsc_query_vport_state_out use a plain u8 field with GENMASK()
and FIELD_GET(), similar to how struct xsc_query_vport_state_in defines
XSC_QUERY_VPORT_OTHER_VPORT and XSC_QUERY_VPORT_VPORT_NUM_MASK?

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Sashiko AI review · https://sashiko.dev/#/patchset/20261104155650.37053-1-tianx@yunsilicon.com?part=2