Re: [PATCH net-next V2 06/13] net/mlx5e: Add data direct RX infrastructure

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Medium] net/mlx5e: SHAMPO header buffer double-sized in
  mlx5e_shampo_hd_per_wqe()
--

commit 65149098852b3b139560ca93742af4a582b969d5
Author: Dragos Tatulea <dtatulea@nvidia.com>

net/mlx5e: Add data direct RX infrastructure

This commit adds RX infrastructure for data direct mode, including a new
RQ state flag, crossing and KSM mkeys, and ICOSQ sizing for KSM UMR WQEs.

> diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c
> index 5caf7820a136b..61a77ee77244a 100644
> --- a/drivers/net/ethernet/mellanox/mlx5/core/en/params.c
> +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/params.c
> @@ -62,6 +62,9 @@ mlx5e_mpwrq_umr_mode(struct mlx5_core_dev *mdev,
>  	bool unaligned = xsk ? xsk->unaligned : false;
>  	bool oversized = false;
>  
> +	if (rqo && rqo->data_direct)
> +		return MLX5E_MPWRQ_UMR_MODE_UNALIGNED;
> +
>  	if (xsk) {
>  		oversized = xsk->chunk_size < (1 << page_shift);
>  		WARN_ON_ONCE(xsk->chunk_size > (1 << page_shift));

[Severity: Medium]
Does switching data-direct SHAMPO RQs to MLX5E_MPWRQ_UMR_MODE_UNALIGNED
cause mlx5e_shampo_hd_per_wq() to double-size the SHAMPO header buffer and
overflow log_headers_buffer_entry_num at maximum ring size?

With 4KB pages, MLX5E_MPWRQ_UMR_MODE_UNALIGNED uses 16-byte KSM entries
instead of 8-byte MTT entries, which halves the WQE size from 256KB to
128KB and doubles wq_size in rq_param->rqc.  However,
mlx5e_shampo_hd_per_wqe() ignores rq_param and passes NULL for rqo:

drivers/net/ethernet/mellanox/mlx5/core/en/params.c:mlx5e_shampo_hd_per_wqe() {
	u16 num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params, NULL));
	u8 log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params, NULL);
	int pkt_per_rsrv = BIT(mlx5e_shampo_get_log_pkt_per_rsrv(params));
	int wqe_size = BIT(log_stride_sz) * num_strides;
    ...
}

Because rqo is NULL, mlx5e_shampo_hd_per_wqe() computes wqe_size for
MLX5E_MPWRQ_UMR_MODE_ALIGNED (256KB) instead of UNALIGNED (128KB), and
mlx5e_shampo_hd_per_wq() multiplies that unhalved hd_per_wqe by the
doubled wq_size from rq_param->rqc.  This allocates twice as many SHAMPO
header pages as needed, and when log_rq_mtu_frames is 13 with sw_mtu <=
1024, hd_per_wq doubles from 32768 to 65536, causing
order_base_2(rq->mpwqe.shampo->hd_per_wq) (16) in mlx5e_create_rq() to
overflow the 4-bit log_headers_buffer_entry_num hardware field to 0.

Passing rqo (or reading log_wqe_num_of_strides and log_wqe_stride_size
from rq_param->rqc) in mlx5e_shampo_hd_per_wqe() would compute the actual
WQE size.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261110183826.2927274-1-tariqt@nvidia.com?part=6