From: fuyao <fuyao@allwinnertech.com>
To: Maxime Ripard <maxime@cerno.tech>
Cc: wens@csie.org, linux-remoteproc@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/2] introduce sunxi hwspinlock
Date: Sat, 21 Nov 2020 22:08:57 +0800 [thread overview]
Message-ID: <20201121140857.GA23438@debian> (raw)
In-Reply-To: <20201120160710.wlkl5cdfqlrym2fj@gilmour>
On Fri, Nov 20, 2020 at 05:07:10PM +0100, Maxime Ripard wrote:
> Hi!
>
> On Thu, Nov 19, 2020 at 02:44:51PM +0800, fuyao@allwinnertech.com wrote:
> > From: fuyao <fuyao@allwinnertech.com>
> >
> > this series add hwspinlock of sunxi. it provides hardware assistance for
> > synchronization between the multiple processors in the system.
> > (Or1k, Cortex-A7, Cortex-A53, Xtensa)
>
> Xtensa? Which SoC has an Xtensa core?
The new Soc named R329 use Xtensa core as the arisc role and audio.
And the hwspinlock is the same as h3 and h6.
Additional, The new RISC-V Soc also use the same hwspinlock.
>
> Unfortunately, there's been a submission of the same driver earlier this week:
> https://lore.kernel.org/lkml/cover.1605693132.git.wilken.gottwalt@posteo.net/
>
> It would be great if you could point out whatever issue there is with
> that patch series (it looks like the retry delay could be useful for
> example).
I will test that submission with arisc next week.
BTW, which sunxi board you used, I want to used the same board with you.
^-^
thanks
--
fuyao
prev parent reply other threads:[~2020-11-21 14:09 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-19 6:44 [PATCH 0/2] introduce sunxi hwspinlock fuyao
2020-11-19 6:44 ` [PATCH 1/2] dt-bindings: hwlock: add sunxi hwlock fuyao
2020-11-19 6:44 ` [PATCH 2/2] hwspinlock: add SUNXI implementation fuyao
2020-11-21 4:01 ` Bjorn Andersson
2020-11-21 14:33 ` fuyao
2020-11-20 16:07 ` [PATCH 0/2] introduce sunxi hwspinlock Maxime Ripard
2020-11-21 14:08 ` fuyao [this message]
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