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[68.147.0.187]) by smtp.gmail.com with ESMTPSA id l189-20020a6225c6000000b005255263a864sm21321486pfl.169.2022.07.04.10.22.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Jul 2022 10:22:06 -0700 (PDT) Date: Mon, 4 Jul 2022 11:22:04 -0600 From: Mathieu Poirier To: Allen-KH Cheng Cc: Bjorn Andersson , Rob Herring , Matthias Brugger , Project_Global_Chrome_Upstream_Group@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-remoteproc@vger.kernel.org, Hsin-Yi Wang Subject: Re: [PATCH v2 1/1] remoteproc: mediatek: enable cache for mt8186 SCP Message-ID: <20220704172204.GB2375750@p14s> References: <20220701121229.22756-1-allen-kh.cheng@mediatek.com> <20220701121229.22756-2-allen-kh.cheng@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220701121229.22756-2-allen-kh.cheng@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: linux-remoteproc@vger.kernel.org On Fri, Jul 01, 2022 at 08:12:29PM +0800, Allen-KH Cheng wrote: > This patch is for enableing cache in SCP. There is not enough space > on the SRAM of SCP. We need to run programs in DRAM. The DRAM power > and latency is much larger than SRAM, so cache is used to mitigate > the negative effects for performance. we set SCP registers for cache s/we/We > size before loading SCP FW. (8KB+8KB) and also adjust ipi_buf_offset > in SRAM from 0x7bdb0 to 0x3BDB0 for enableing cache. s/0x3BDB0/0x3bdb0 s/enableing/enabling > > This patch was tested on MediaTek mt8186. > If we keep the above statement it will be in the kernel's changelog for ever. Comments such as this one are usually found in the cover letter or between "---" lines after the SoB. > Signed-off-by: Allen-KH Cheng > --- > drivers/remoteproc/mtk_scp.c | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c > index 47b2a40e1b4a..5b2ad789e720 100644 > --- a/drivers/remoteproc/mtk_scp.c > +++ b/drivers/remoteproc/mtk_scp.c > @@ -401,6 +401,14 @@ static int mt8186_scp_before_load(struct mtk_scp *scp) > writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_P1); > writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_p2); > > + /* > + * Set I-cache and D-cache size before loading SCP FW. > + * SCP SRAM logical address may change when cache size setting differs. > + */ > + writel(MT8183_SCP_CACHE_CON_WAYEN | MT8183_SCP_CACHESIZE_8KB, > + scp->reg_base + MT8183_SCP_CACHE_CON); > + writel(MT8183_SCP_CACHESIZE_8KB, scp->reg_base + MT8183_SCP_DCACHE_CON); > + > return 0; > } > > @@ -943,7 +951,7 @@ static const struct mtk_scp_of_data mt8186_of_data = { > .scp_da_to_va = mt8183_scp_da_to_va, > .host_to_scp_reg = MT8183_HOST_TO_SCP, > .host_to_scp_int_bit = MT8183_HOST_IPC_INT_BIT, > - .ipi_buf_offset = 0x7bdb0, > + .ipi_buf_offset = 0x3bdb0, > }; I have made the above corrections and applied this patch. Thanks, Mathieu > > static const struct mtk_scp_of_data mt8192_of_data = { > -- > 2.18.0 >