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AFNElJ87E3xEIL+ZaC1ErEvP8Rd6OUI2UJroQQtFkG+3wsE9BtSx+KmCQAMtrMDdzwvkiIjA0QbG6uuqNPR32EZFCiRg@vger.kernel.org X-Received: by 2002:a05:7300:7316:b0:2c0:e404:8b08 with SMTP id 5a478bee46e88-2ed0a19128emr207103eec.29.1777320764913; Mon, 27 Apr 2026 13:12:44 -0700 (PDT) X-Received: by 2002:a05:7300:7316:b0:2c0:e404:8b08 with SMTP id 5a478bee46e88-2ed0a19128emr207074eec.29.1777320764314; Mon, 27 Apr 2026 13:12:44 -0700 (PDT) Received: from mail.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ed09fb6b7fsm437136eec.10.2026.04.27.13.12.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 13:12:43 -0700 (PDT) From: Kamal Dasu To: andersson@kernel.org, robh@kernel.org Cc: krzysztof.kozlowski@linaro.org, conor+dt@kernel.org, baolin.wang@linux.alibaba.com, florian.fainelli@broadcom.com, bcm-kernel-feedback-list@broadcom.com, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Kamal Dasu Subject: [PATCH v7 1/3] dt-bindings: hwlock: Adding brcmstb-hwspinlock support Date: Mon, 27 Apr 2026 16:12:31 -0400 Message-Id: <20260427201233.380314-2-kamal.dasu@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260427201233.380314-1-kamal.dasu@broadcom.com> References: <20260427201233.380314-1-kamal.dasu@broadcom.com> Precedence: bulk X-Mailing-List: linux-remoteproc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-DetectorID-Processed: b00c1d49-9d2e-4205-b15f-d015386d3d5e The Broadcom settop SoCs have hardware semaphores as part of the "sundry" IP block which has other controls that do not belong anywhere else e.g. pin/mux controls, SoC identification, drive strength, reset controls, and other misc bits are part of this block. Adding brcmstb-hwspinlock bindings which allows the hwspinlock driver to iomap only the 16 hardware semaphore registers that are part of all settop SoCs. The semaphore registers are based on the BCM7038 SoC where they were first introduced in settop chips. Signed-off-by: Kamal Dasu Reviewed-by: Krzysztof Kozlowski --- .../brcm,bcm7038-sun-top-ctrl-semaphore.yaml | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwlock/brcm,bcm7038-sun-top-ctrl-semaphore.yaml diff --git a/Documentation/devicetree/bindings/hwlock/brcm,bcm7038-sun-top-ctrl-semaphore.yaml b/Documentation/devicetree/bindings/hwlock/brcm,bcm7038-sun-top-ctrl-semaphore.yaml new file mode 100644 index 000000000000..552f334256b5 --- /dev/null +++ b/Documentation/devicetree/bindings/hwlock/brcm,bcm7038-sun-top-ctrl-semaphore.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwlock/brcm,bcm7038-sun-top-ctrl-semaphore.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Settop Sundry Block Hardware Semaphore + +description: + Broadcom settop SoCs contain 16 hardware semaphore registers + (SEMAPHORE_0 through SEMAPHORE_15) that provide hardware-arbitrated + mutual exclusion between drivers running on the SoC. + + The semaphore registers belong to the sundry hardware block. The + node describes the semaphore register range carved out of the larger + sundry block address space. + +maintainers: + - Kamal Dasu + +properties: + compatible: + const: brcm,bcm7038-sun-top-ctrl-semaphore + + "#hwlock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - "#hwlock-cells" + +additionalProperties: false + +examples: + - | + hwlock@404038 { + compatible = "brcm,bcm7038-sun-top-ctrl-semaphore"; + reg = <0x404038 0x40>; + #hwlock-cells = <1>; + }; -- 2.34.1