* [PATCH 0/2] arm64: dts: renesas: Increase CANFD clock rates
@ 2025-08-13 13:37 Geert Uytterhoeven
2025-08-13 13:37 ` [PATCH 1/2] arm64: dts: renesas: rcar-gen3: " Geert Uytterhoeven
2025-08-13 13:37 ` [PATCH 2/2] arm64: dts: renesas: rzg2: " Geert Uytterhoeven
0 siblings, 2 replies; 3+ messages in thread
From: Geert Uytterhoeven @ 2025-08-13 13:37 UTC (permalink / raw)
To: Magnus Damm, Biju Das
Cc: linux-renesas-soc, linux-arm-kernel, Geert Uytterhoeven
Hi all,
Currently, all R-Car Gen3 and RZ/G2 .dtsi files configure the CANFD core
clocks to 40 MHz, which limits CAN-FD data transfer rates to 4 Mbps.
However, all R-Car Gen3 and RZ/G2 SoCs except for R-Car D3 support CANFD
clock rates up to 80 MHz.
Now the R-Car CAN-FD driver has gained support for Transceiver Delay
Compensation in v6.17-rc1, increase all appropriate CANFD clock rates to
the documented maximum, to support data rates up to 8 Mbps.
The R-Car Gen3 boards that have CAN-FD enabled use CAN transceivers
that support transfer rates up to 8 (Ebisu) or 5 (Condor(-I), Eagle)
Mbps. None of the RZ/G2 boards have CAN-FD enabled.
The Draak board, and some of the RZ/G2 boards have CAN enabled instead
of CAN-FD. None of these are affected by this series, as they either
rely on the default value of zero for the "renesas,can-clock-select"
property, or configure it explicitly to zero, thus not using the CANFD
core clock as CAN clock source.
All .dtsi files for SoCs in the RZ/G2L family configure the P0_DIV2
clock to 50 Mhz, which should be sufficient for the maximum supported
transfer rates of 4 Mbps (my board has no CAN transceiver mounted...).
RZ/G3E already configures its can_clk to 80 MHz.
This series has been tested on Ebisu-4D (R-Car E3).
I plan to queue it in renesas-devel for v6.18.
Thanks for your comments!
Geert Uytterhoeven (2):
arm64: dts: renesas: rcar-gen3: Increase CANFD clock rates
arm64: dts: renesas: rzg2: Increase CANFD clock rates
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a77951.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 2 +-
11 files changed, 11 insertions(+), 11 deletions(-)
--
2.43.0
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 1/2] arm64: dts: renesas: rcar-gen3: Increase CANFD clock rates
2025-08-13 13:37 [PATCH 0/2] arm64: dts: renesas: Increase CANFD clock rates Geert Uytterhoeven
@ 2025-08-13 13:37 ` Geert Uytterhoeven
2025-08-13 13:37 ` [PATCH 2/2] arm64: dts: renesas: rzg2: " Geert Uytterhoeven
1 sibling, 0 replies; 3+ messages in thread
From: Geert Uytterhoeven @ 2025-08-13 13:37 UTC (permalink / raw)
To: Magnus Damm, Biju Das
Cc: linux-renesas-soc, linux-arm-kernel, Geert Uytterhoeven
Currently, all R-Car Gen3 .dtsi files configure the CANFD core clocks to
40 MHz, which limits CAN-FD data transfer rates to 4 Mbps. However, all
R-Car Gen3 SoCs except for R-Car D3 support CANFD clock rates up to 80
MHz.
Now the R-Car CAN-FD driver has gained support for Transceiver Delay
Compensation, increase all appropriate CANFD clock rates to the
documented maximum, to support data rates up to 8 Mbps.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a77951.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
index 6ee9cdeb5a3ab478..c389ebc7e6ce8f00 100644
--- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
@@ -1373,7 +1373,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
+ assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
index a323ac47ca70f3db..6d039019905ded0a 100644
--- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi
@@ -1245,7 +1245,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
+ assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
index 49f6d31c5903b8b3..1637b534fc68b19d 100644
--- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi
@@ -1245,7 +1245,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
+ assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 136a22ca50b78674..353a771870893994 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -1108,7 +1108,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77965_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
+ assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index 01744496805c3200..e7a5800bf74216fa 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -568,7 +568,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
+ assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index f7e506ad7a211a57..964aa14f3e65d925 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -621,7 +621,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
+ assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 6b8742045836b9b9..e16ede6eb3791ad1 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -1061,7 +1061,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
+ assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
--
2.43.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] arm64: dts: renesas: rzg2: Increase CANFD clock rates
2025-08-13 13:37 [PATCH 0/2] arm64: dts: renesas: Increase CANFD clock rates Geert Uytterhoeven
2025-08-13 13:37 ` [PATCH 1/2] arm64: dts: renesas: rcar-gen3: " Geert Uytterhoeven
@ 2025-08-13 13:37 ` Geert Uytterhoeven
1 sibling, 0 replies; 3+ messages in thread
From: Geert Uytterhoeven @ 2025-08-13 13:37 UTC (permalink / raw)
To: Magnus Damm, Biju Das
Cc: linux-renesas-soc, linux-arm-kernel, Geert Uytterhoeven
Currently, all RZ/G2 .dtsi files configure the CANFD core clocks to 40
MHz, which limits CAN-FD data transfer rates to 4 Mbps. However, all
RZ/G2 SoCs support CANFD clock rates up to 80 MHz.
Now the R-Car CAN-FD driver has gained support for Transceiver Delay
Compensation, increase all appropriate CANFD clock rates to the
documented maximum, to support data rates up to 8 Mbps.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 2 +-
arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index c8b87aed92a368b1..6b737d91b320f483 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -1186,7 +1186,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A774A1_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
+ assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index f2fc2a2035a1d491..3f15d656215e15e8 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -1070,7 +1070,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
+ assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 530ffd29cf13da00..55df063cb32327c2 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1029,7 +1029,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
+ assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
index e4dbda8c34d9eaef..5d730b488d46f24b 100644
--- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi
@@ -1298,7 +1298,7 @@ canfd: can@e66c0000 {
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>;
- assigned-clock-rates = <40000000>;
+ assigned-clock-rates = <80000000>;
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
--
2.43.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2025-08-13 13:37 UTC | newest]
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2025-08-13 13:37 [PATCH 0/2] arm64: dts: renesas: Increase CANFD clock rates Geert Uytterhoeven
2025-08-13 13:37 ` [PATCH 1/2] arm64: dts: renesas: rcar-gen3: " Geert Uytterhoeven
2025-08-13 13:37 ` [PATCH 2/2] arm64: dts: renesas: rzg2: " Geert Uytterhoeven
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