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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1755027339; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gEO4of1tDk5pyESbxLhghGpcN4wW9jV8MI6Qe8anx2U=; b=HoQrJVxXU0kGqI2fNtwdWcE3VHts9InPlYRCZxZJ/Ly5JhQ2NxGI1AlQROzCDDcPX8fdzk 0vHME8Ati2+F082o74xx2cEqHKG75FR8EcICBY5odnd5Lm0RS/B7Ptz5xj0QGY5hoErV15 PyI6A49Eb+GFx94Rzf3md0EElKgOjMD9za9kxm0s7QNziyIwegzvNmVt2SKOQUqEDnmcoU o6j/5rNhW9ErE3AoljkRGsLZmkaG/kA7s9OFzIVSmypfEdhHc3hmvlAf4V5yKNyyPsn4TN qKu9IjIM5E3aAkiMEb4m/Uf+U00RtGwXyPPvGBw2k5xK5W6/uOQ1pllkNLe+sA== Date: Tue, 12 Aug 2025 21:35:36 +0200 Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH 2/4] drm/rcar-du: dsi: Remove fixed PPI lane count setup To: Tomi Valkeinen , Marek Vasut , dri-devel@lists.freedesktop.org Cc: David Airlie , Geert Uytterhoeven , Kieran Bingham , Laurent Pinchart , Maarten Lankhorst , Magnus Damm , Maxime Ripard , Simona Vetter , Thomas Zimmermann , linux-renesas-soc@vger.kernel.org References: <20250608142636.54033-1-marek.vasut+renesas@mailbox.org> <20250608142636.54033-3-marek.vasut+renesas@mailbox.org> <64b49da6-15ae-45e1-a4af-c1f08f80cf3a@ideasonboard.com> <87cc32a7-fe1d-4d8d-b793-e3bb7e12fb7d@ideasonboard.com> Content-Language: en-US From: Marek Vasut In-Reply-To: <87cc32a7-fe1d-4d8d-b793-e3bb7e12fb7d@ideasonboard.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-MBO-RS-ID: 7daa446b7a83f7697af X-MBO-RS-META: wudcw1kwc87tbfy16g5yq7id47pfsahx X-Rspamd-Queue-Id: 4c1hYn40dRz9sZK On 8/12/25 3:30 PM, Tomi Valkeinen wrote: Hi, >>> diff --git a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h >>> index b3e57217ae63..cefa7e92b5b8 100644 >>> --- a/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h >>> +++ b/drivers/gpu/drm/renesas/rcar-du/rcar_mipi_dsi_regs.h >>> @@ -80,10 +80,7 @@ >>> * PHY-Protocol Interface (PPI) Registers >>> */ >>> #define PPISETR 0x700 >>> -#define PPISETR_DLEN_0 (0x1 << 0) >>> -#define PPISETR_DLEN_1 (0x3 << 0) >>> -#define PPISETR_DLEN_2 (0x7 << 0) >>> -#define PPISETR_DLEN_3 (0xf << 0) >>> +#define PPISETR_DLEN_MASK (0xf << 0) >>> #define PPISETR_CLEN BIT(8) >> >> Looks fine, but do you know what the TXSETR register does? It also has >> LANECNT, but I don't see the driver touching that register at all. >> TXSETR:LANECNT default value is 3 (4 lanes), which matches with the old >> hardcoded behavior for PPISETR... So I wonder if that register should >> also be set? > > Ah, never mind, I now saw the patch 3 =). But should it be before patch > 2? Hmm, I guess that ordering is no better. Should they be combined into > "support 1,2,3 datalanes" patch? I think each patch fixes slighly different issue, even if the issues are related. I tried to keep the issue description in each patch commit message for posterity. I can squash them if you think that's better, I don't mind either way.