From: Simon Horman <horms@verge.net.au>
To: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Cc: bhelgaas@google.com, linux-pci@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH] pcie-rcar: try setting PCIe speed to 5 GT/s at boot
Date: Tue, 13 Sep 2016 17:19:26 +0200 [thread overview]
Message-ID: <20160913151926.GC25005@verge.net.au> (raw)
In-Reply-To: <6896977.DKiraAXap6@wasted.cogentembedded.com>
On Wed, Sep 07, 2016 at 11:22:14PM +0300, Sergei Shtylyov wrote:
> From: Grigory Kletsko <grigory.kletsko@cogentembedded.com>
>
> Initially, the PCIe link speed is set up only at 2.5 GT/s.
> For better performance, we're trying to increase link speed to 5 GT/s.
>
> [Sergei Shtylyov: indented the macro definitions with tabs, renamed the
> SPCHG register bits for consistency, renamed the link speed field/values,
> fixed too long lines, fixed redundancy in clearing the MACSR register bits,
> fixed grammar/typos in the comments/messages, removed unrelated/useless
> changes, fixed bugs in rcar_rwm32() calls done to set the bits, removed
> unneeded braces, removed non-informative comment, reworded the patch
> summary/description.]
>
> Signed-off-by: Grigory Kletsko <grigory.kletsko@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
next prev parent reply other threads:[~2016-09-13 15:19 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-07 20:22 [PATCH] pcie-rcar: try setting PCIe speed to 5 GT/s at boot Sergei Shtylyov
2016-09-13 15:19 ` Simon Horman [this message]
2016-09-14 20:54 ` Bjorn Helgaas
2016-09-20 18:13 ` Sergei Shtylyov
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