From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf0-f53.google.com ([209.85.215.53]:34002 "EHLO mail-lf0-f53.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757383AbdCUUEx (ORCPT ); Tue, 21 Mar 2017 16:04:53 -0400 Received: by mail-lf0-f53.google.com with SMTP id z15so71290964lfd.1 for ; Tue, 21 Mar 2017 13:04:52 -0700 (PDT) From: Sergei Shtylyov Message-Id: <20170321200448.051326718@cogentembedded.com> Date: Tue, 21 Mar 2017 23:04:45 +0300 To: Simon Horman , Rob Herring , Mark Rutland , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org Cc: Magnus Damm , Russell King , linux-arm-kernel@lists.infradead.org, Sergei Shtylyov Subject: [PATCH 2/2] ARM: dts: r8a7792: add IMR-L[S]X3 support MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Disposition: inline; filename=ARM-dts-r8a7792-add-IMR-L-S-X3-support.patch Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: Describe the IMR-LX3 and 6 IMR-LSX3 devices in the R8A7792 device tree. Based on the original patch by Roman Meshkevich Signed-off-by: Sergei Shtylyov --- arch/arm/boot/dts/r8a7792.dtsi | 63 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) Index: renesas/arch/arm/boot/dts/r8a7792.dtsi =================================================================== --- renesas.orig/arch/arm/boot/dts/r8a7792.dtsi +++ renesas/arch/arm/boot/dts/r8a7792.dtsi @@ -734,6 +734,69 @@ status = "disabled"; }; + imr-lsx3@fe840000 { + compatible = "renesas,r8a7792-imr-lsx3", + "renesas,imr-lsx3"; + reg = <0 0xfe840000 0 0x2000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_IMR_LSX3_0>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + imr-lsx3@fe850000 { + compatible = "renesas,r8a7792-imr-lsx3", + "renesas,imr-lsx3"; + reg = <0 0xfe850000 0 0x2000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_IMR_LSX3_1>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + imr-lsx3@fe860000 { + compatible = "renesas,r8a7792-imr-lsx3", + "renesas,imr-lsx3"; + reg = <0 0xfe860000 0 0x2000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_IMR_LSX3_2>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + imr-lsx3@fe870000 { + compatible = "renesas,r8a7792-imr-lsx3", + "renesas,imr-lsx3"; + reg = <0 0xfe870000 0 0x2000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_IMR_LSX3_3>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + imr-lsx3@fe880000 { + compatible = "renesas,r8a7792-imr-lsx3", + "renesas,imr-lsx3"; + reg = <0 0xfe880000 0 0x2000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_IMR_LSX3_4>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + imr-lsx3@fe890000 { + compatible = "renesas,r8a7792-imr-lsx3", + "renesas,imr-lsx3"; + reg = <0 0xfe890000 0 0x2000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_IMR_LSX3_5>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + imr-lx3@fead0000 { + compatible = "renesas,r8a7792-imr-lx3", + "renesas,imr-lx3"; + reg = <0 0xfead0000 0 0x2000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_IMR_LX3>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + vsp1@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>;