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bh=Yjpl5P036SzcXdZApIpw3yupiX65ZpgCi/JEAYydfII=; b=YiiO+s0d37LZ9m5y4kzMD1QTAn+DwVlPjGwKIHBc4N2yry3xKv7QSlfFBbzDpMQWJ0/KaI 9I74izbx3XPoxTdKtc+mKlEAMlJkoVrLiwgnCCPFBM4c37qmjOPwEJt3z+ENTvZ8yk+U+e 01DMMY2JTqGlpI3eqBVSuf8MDG4671+9+FWDqCsG8W+jLyh1mRiGBWH2vWoo4JPCfYnaLf gSB2Hywk5IAtJl82BvQw2ctOjjGVETk4+cr5an67pKSjMctAv6N6b0oniLcSJ+TWlf7zGI 1bIqzVvWCk3NuKd8sHYTip5+CXeNopQy7ODoKPEqBI+ARcJxpZR+SEFiLMXwCA== Date: Wed, 30 Jul 2025 11:17:55 +0200 From: Herve Codina To: Rob Herring Cc: Hoan Tran , Linus Walleij , Bartosz Golaszewski , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm , Saravana Kannan , Serge Semin , Phil Edworthy , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Miquel Raynal , Thomas Petazzoni Subject: Re: [PATCH 1/6] dt-bindings: gpio: snps,dw-apb: Add support for Renesas RZ/N1 Message-ID: <20250730111755.24aa16b2@bootlin.com> In-Reply-To: <20250729181151.GA530390-robh@kernel.org> References: <20250725152618.32886-1-herve.codina@bootlin.com> <20250725152618.32886-2-herve.codina@bootlin.com> <20250729181151.GA530390-robh@kernel.org> Organization: Bootlin X-Mailer: Claws Mail 4.3.1 (GTK 3.24.43; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: linux-renesas-soc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgdeljeehhecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhepfffhvfevuffkjghfohfogggtgfesthekredtredtjeenucfhrhhomhepjfgvrhhvvgcuvehoughinhgruceohhgvrhhvvgdrtghoughinhgrsegsohhothhlihhnrdgtohhmqeenucggtffrrghtthgvrhhnpeeviefffeegiedtleelieeghfejleeuueevkeevteegffehledtkeegudeigffgvdenucfkphepledtrdekledrudeifedruddvjeenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepihhnvghtpeeltddrkeelrdduieefrdduvdejpdhhvghloheplhhotggrlhhhohhsthdpmhgrihhlfhhrohhmpehhvghrvhgvrdgtohguihhnrgessghoohhtlhhinhdrtghomhdpnhgspghrtghpthhtohepudejpdhrtghpthhtoheprhhosghhsehkvghrnhgvlhdrohhrghdprhgtphhtthhopehhohgrnhesohhsrdgrmhhpvghrvggtohhmphhuthhinhhgrdgtohhmpdhrtghpthhtoheplhhinhhushdrfigrlhhlvghijheslhhinhgrrhhordhorhhgpdhrtghpthhtohepsghrghhlsegsghguvghvrdhplhdprhgtphhtthhopehkrhiikhdoughtsehkvghrnhgvlhdrohhrghdprhgtphhtthhopegtohhnohhrodgut heskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepghgvvghrthdorhgvnhgvshgrshesghhlihguvghrrdgsvgdprhgtphhtthhopehmrghgnhhushdruggrmhhmsehgmhgrihhlrdgtohhm X-GND-Sasl: herve.codina@bootlin.com Hi Rob, On Tue, 29 Jul 2025 13:11:51 -0500 Rob Herring wrote: > On Fri, Jul 25, 2025 at 05:26:10PM +0200, Herve Codina wrote: > > The RZ/N1 SoCs uses the Synopsys DesignWare IP to handle GPIO blocks. > > > > Add RZ/N1 SoC and family compatible strings. > > Why? Yes, that's policy, but so far we avoided it on this IP. Perhaps > because it is simple enough. So what's different here? I've just followed Renesas policy. Nothing other than this policy justifies the change and so, I can remove the Renesas compatible strings. In other words, I can simply remove this patch. Best regards, Hervé