[PATCH 0/6] gpio: renesas: Add support for GPIO and related interrupts in RZ/N1 SoC

[PATCH 0/6] gpio: renesas: Add support for GPIO and related interrupts in RZ/N1 SoC

[Herve Codina]

Hi,

This series adds support for GPIO and GPIO IRQ mux available in the
RZ/N1 SoCs.

The first two patches of the series add support for GPIO (binding update
and device-tree description).

Other patches are related to GPIO interrupts and GPIO IRQ multiplexer.

In the RZ/N1 SoCs, GPIO interrupts are wired to a GPIO IRQ multiplexer.

This multiplexer does nothing but select 8 GPIO IRQ lines out of the 96
available to wire them to the GIC input lines.

One upstreaming attempt have been done previously by Phil Edworthy [1]
but the series has never been applied.

Based on my understanding, I have fully reworked the driver proposed by
Phil and removed the IRQ domain. Indeed, the device doesn't handle
interrupts. It just routes signals.

Also, as an interrupt-map property is used, the driver cannot be
involved as an interrupt controller itself. It is a nexus node.

With that in mind, patch 3 is related to the binding, patch 4 introduces
an helper to parse the interrupt-map property. This parsing is needed by
the driver. Indeed, the lines routing is defined by the interrupt-map
property and the driver needs to set registers to apply this routing.

The last two patches are the driver itself and the RZ/N1 device-tree
description update to have the support for the GPIO interrupts.

[1] https://lore.kernel.org/all/20190219155511.28507-1-phil.edworthy@renesas.com/

Best regards,
Hervé

Herve Codina (6):
  dt-bindings: gpio: snps,dw-apb: Add support for Renesas RZ/N1
  ARM: dts: r9a06g032: Add GPIO controllers
  dt-bindings: soc: renesas: Add the Renesas RZ/N1 GPIO Interrupt
    Multiplexer
  of/irq: Introduce of_irq_foreach_imap
  soc: renesas: Add support for Renesas RZ/N1 GPIO Interrupt Multiplexer
  ARM: dts: r9a06g032: Add support for GPIO interrupts

 .../bindings/gpio/snps,dw-apb-gpio.yaml       |   8 +-
 .../soc/renesas/renesas,rzn1-gpioirqmux.yaml  |  99 ++++++++++
 arch/arm/boot/dts/renesas/r9a06g032.dtsi      | 172 ++++++++++++++++++
 drivers/of/irq.c                              |  70 +++++++
 drivers/soc/renesas/Kconfig                   |   4 +
 drivers/soc/renesas/Makefile                  |   1 +
 drivers/soc/renesas/rzn1_irqmux.c             | 169 +++++++++++++++++
 include/linux/of_irq.h                        |  11 ++
 8 files changed, 533 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml
 create mode 100644 drivers/soc/renesas/rzn1_irqmux.c

-- 
2.50.1

[PATCH 1/6] dt-bindings: gpio: snps,dw-apb: Add support for Renesas RZ/N1

[Herve Codina]

The RZ/N1 SoCs uses the Synopsys DesignWare IP to handle GPIO blocks.

Add RZ/N1 SoC and family compatible strings.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
 .../devicetree/bindings/gpio/snps,dw-apb-gpio.yaml        | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml
index ab2afc0e4153..ceb71b5ac688 100644
--- a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml
@@ -20,7 +20,13 @@ properties:
     pattern: "^gpio@[0-9a-f]+$"
 
   compatible:
-    const: snps,dw-apb-gpio
+    oneOf:
+      - const: snps,dw-apb-gpio
+      - items:
+          - enum:
+              - renesas,r9a06g032-gpio
+          - const: renesas,rzn1-gpio
+          - const: snps,dw-apb-gpio
 
   "#address-cells":
     const: 1
-- 
2.50.1

[PATCH 2/6] ARM: dts: r9a06g032: Add GPIO controllers

[Herve Codina]

Add GPIO controllers (Synosys DesignWare IPs) available in the
r9a06g032 (RZ/N1D) SoC.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
 arch/arm/boot/dts/renesas/r9a06g032.dtsi | 127 +++++++++++++++++++++++
 1 file changed, 127 insertions(+)

diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
index 80ad1fdc77a0..7f71c01af409 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
@@ -499,6 +499,133 @@ gic: interrupt-controller@44101000 {
 				<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
 		};
 
+		/*
+		 * The GPIO mapping to the corresponding pins is not obvious.
+		 * See the hardware documentation for details.
+		 */
+		gpio0: gpio@5000b000 {
+			compatible = "renesas,r9a06g032-gpio", "renesas,rzn1-gpio", "snps,dw-apb-gpio";
+			reg = <0x5000b000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&sysctrl R9A06G032_HCLK_GPIO0>;
+			clock-names = "bus";
+			status = "disabled";
+
+			/* GPIO0a[0]      connected to pin  GPIO0      */
+			/* GPIO0a[1..2]   connected to pins GPIO3..4   */
+			/* GPIO0a[3..4]   connected to pins GPIO9..10  */
+			/* GPIO0a[5]      connected to pin  GPIO12     */
+			/* GPIO0a[6..7]   connected to pins GPIO15..16 */
+			/* GPIO0a[8..9]   connected to pins GPIO21..22 */
+			/* GPIO0a[10]     connected to pin  GPIO24     */
+			/* GPIO0a[11..12] connected to pins GPIO27..28 */
+			/* GPIO0a[13..14] connected to pins GPIO33..34 */
+			/* GPIO0a[15]     connected to pin  GPIO36     */
+			/* GPIO0a[16..17] connected to pins GPIO39..40 */
+			/* GPIO0a[18..19] connected to pins GPIO45..46 */
+			/* GPIO0a[20]     connected to pin  GPIO48     */
+			/* GPIO0a[21..22] connected to pins GPIO51..52 */
+			/* GPIO0a[23..24] connected to pins GPIO57..58 */
+			/* GPIO0a[25..31] connected to pins GPIO62..68 */
+			gpio0a: gpio@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				bank-name = "gpio0a";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+
+			/* GPIO0b[0..1]   connected to pins GPIO1..2   */
+			/* GPIO0b[2..5]   connected to pins GPIO5..8   */
+			/* GPIO0b[6]      connected to pin  GPIO11     */
+			/* GPIO0b[7..8]   connected to pins GPIO13..14 */
+			/* GPIO0b[9..12]  connected to pins GPIO17..20 */
+			/* GPIO0b[13]     connected to pin  GPIO23     */
+			/* GPIO0b[14..15] connected to pins GPIO25..26 */
+			/* GPIO0b[16..19] connected to pins GPIO29..32 */
+			/* GPIO0b[20]     connected to pin  GPIO35     */
+			/* GPIO0b[21..22] connected to pins GPIO37..38 */
+			/* GPIO0b[23..26] connected to pins GPIO41..44 */
+			/* GPIO0b[27]     connected to pin  GPIO47     */
+			/* GPIO0b[28..29] connected to pins GPIO49..50 */
+			/* GPIO0b[30..31] connected to pins GPIO53..54 */
+			gpio0b: gpio@1 {
+				compatible = "snps,dw-apb-gpio-port";
+				bank-name = "gpio0b";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <1>;
+			};
+		};
+
+		gpio1: gpio@5000c000 {
+			compatible = "renesas,r9a06g032-gpio", "renesas,rzn1-gpio", "snps,dw-apb-gpio";
+			reg = <0x5000c000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&sysctrl R9A06G032_HCLK_GPIO1>;
+			clock-names = "bus";
+			status = "disabled";
+
+			/* GPIO1a[0..4]  connected to pins GPIO69..73 */
+			/* GPIO1a[5..31] connected to pins GPIO95..121 */
+			gpio1a: gpio@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				bank-name = "gpio1a";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+
+			/* GPIO1b[0..1]   connected to pins GPIO55..56 */
+			/* GPIO1b[2..4]   connected to pins GPIO59..61 */
+			/* GPIO1b[5..25]  connected to pins GPIO74..94 */
+			/* GPIO1b[26..31] connected to pins GPIO150..155 */
+			gpio1b: gpio@1 {
+				compatible = "snps,dw-apb-gpio-port";
+				bank-name = "gpio1b";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <1>;
+			};
+		};
+
+		gpio2: gpio@5000d000 {
+			compatible = "renesas,r9a06g032-gpio", "renesas,rzn1-gpio", "snps,dw-apb-gpio";
+			reg = <0x5000d000 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&sysctrl R9A06G032_HCLK_GPIO2>;
+			clock-names = "bus";
+			status = "disabled";
+
+			/* GPIO2a[0..27]  connected to pins GPIO122..149 */
+			/* GPIO2a[28..31] connected to pins GPIO156..159 */
+			gpio2a: gpio@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				bank-name = "gpio2a";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				reg = <0>;
+			};
+
+			/* GPIO2b[0..9] connected to pins GPIO160..169 */
+			gpio2b: gpio@1 {
+				compatible = "snps,dw-apb-gpio-port";
+				bank-name = "gpio2b";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <10>;
+				reg = <1>;
+			};
+		};
+
 		can0: can@52104000 {
 			compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
 			reg = <0x52104000 0x800>;
-- 
2.50.1

[PATCH 3/6] dt-bindings: soc: renesas: Add the Renesas RZ/N1 GPIO Interrupt Multiplexer

[Herve Codina]

On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those
interruption lines are multiplexed by the GPIO Interrupt Multiplexer in
order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.

The GPIO interrupt multiplexer IP does nothing but select 8 GPIO
IRQ lines out of the 96 available to wire them to the GIC input lines.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
 .../soc/renesas/renesas,rzn1-gpioirqmux.yaml  | 99 +++++++++++++++++++
 1 file changed, 99 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml
new file mode 100644
index 000000000000..d2b380f15be7
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/renesas/renesas,rzn1-gpioirqmux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/N1 SoCs GPIO Interrupt Multiplexer
+
+description: |
+   The Renesas RZ/N1 GPIO Interrupt Multiplexer multiplexes GPIO interrupt
+   lines to the interrupt controller available in the SoC.
+
+   It selects up to 8 of the 96 GPIO interrupt lines available and connect them
+   to 8 output interrupt lines.
+
+maintainers:
+  - Herve Codina <herve.codina@bootlin.com>
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - renesas,r9a06g032-gpioirqmux
+      - const: renesas,rzn1-gpioirqmux
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    minItems: 8
+    maxItems: 8
+    description:
+      Output interrupt lines
+
+  "#address-cells":
+    const: 0
+
+  "#interrupt-cells":
+    const: 1
+
+  interrupt-map-mask:
+    items:
+      - const: 0x7f
+
+  interrupt-map:
+    description:
+      Specifies the mapping from external GPIO interrupt lines to the output
+      interrupts.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - "#address-cells"
+  - "#interrupt-cells"
+  - interrupt-map-mask
+  - interrupt-map
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    gic: interrupt-controller {
+        interrupt-controller;
+        #interrupt-cells = <3>;
+    };
+
+    interrupt-controller@51000480 {
+        compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux";
+        reg = <0x51000480 0x20>;
+        interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+        #address-cells = <0>;
+        #interrupt-cells = <1>;
+        interrupt-map-mask = <0x7f>;
+        /*
+         * The child interrupt number is computed using the following formula:
+         *    gpio_bank * 32 + gpio_number
+         *
+         * with:
+         *    - gpio_bank: The GPIO bank number
+         *          - 0 for GPIO0A,
+         *          - 1 for GPIO1A,
+         *          - 2 for GPIO2A
+         *    - gpio_number: Number of the gpio in the bank (0..31)
+         */
+        interrupt-map =
+            <32 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1A.0 */
+            <89 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* GPIO2A.25 */
+            <9 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; /* GPIO0A.9 */
+    };
-- 
2.50.1

[PATCH 4/6] of/irq: Introduce of_irq_foreach_imap

[Herve Codina]

of_irq_foreach_imap is an iterator designed to help a driver to parse
an interrupt-map property.

Indeed some drivers need to know details about the interrupt mapping
described in the device-tree in order to set internal registers
accordingly.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
 drivers/of/irq.c       | 70 ++++++++++++++++++++++++++++++++++++++++++
 include/linux/of_irq.h | 11 +++++++
 2 files changed, 81 insertions(+)

diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index f8ad79b9b1c9..863b31eb3c1a 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -157,6 +157,76 @@ const __be32 *of_irq_parse_imap_parent(const __be32 *imap, int len, struct of_ph
 	return imap;
 }
 
+/**
+ * of_irq_foreach_imap - Iterate through interrupt-map items
+ * @np: device node where interrupt-map is available
+ * @func: function called on each interrupt-map items
+ * @data: data passe to @func
+ *
+ * This function iterates through interrupt-map items and calls @func on each
+ * item. The parent interrupt described in the interrupt-map item is parsed
+ * and passed to @func using a pointer to a struct of_phandle_args.
+ * Also the imap raw value is passed in order to allow @func to look at other
+ * values of the interrupt-map (child unit address and child interrupt
+ * specificer)
+ *
+ * If @func returns an error, the iteration stops and this error is returned.
+ */
+int of_irq_foreach_imap(struct device_node *np,
+			int (*func)(void *data,
+				    const __be32 *imap,
+				    const struct of_phandle_args *parent_args),
+			void *data)
+{
+	const __be32 *imap, *imap_end, *imap_parent, *imap_next;
+	struct of_phandle_args parent_args;
+	u32 tmp, parent_offset;
+	int imaplen;
+	int ret;
+
+	/*
+	 * parent_offset is the offset where the parent part is starting.
+	 * In other words, the offset where the parent interrupt controller
+	 * phandle is present.
+	 *
+	 * Compute this offset (child #interrupt-cells + child #address-cells)
+	 */
+	parent_offset = of_bus_n_addr_cells(np);
+
+	ret = of_property_read_u32(np, "#interrupt-cells", &tmp);
+	if (ret)
+		return ret;
+
+	parent_offset += tmp;
+
+	imap = of_get_property(np, "interrupt-map", &imaplen);
+	if (!imap)
+		return -ENOENT;
+
+	imaplen /= sizeof(*imap);
+	imap_end = imap + imaplen;
+
+	while (imap + parent_offset + 1 < imap_end) {
+		imap_parent = imap + parent_offset;
+
+		imap_next = of_irq_parse_imap_parent(imap_parent,
+						     imap_end - imap_parent,
+						     &parent_args);
+		if (!imap_next)
+			return -EINVAL;
+
+		ret = func(data, imap, &parent_args);
+		of_node_put(parent_args.np);
+		if (ret)
+			return ret;
+
+		imap = imap_next;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(of_irq_foreach_imap);
+
 /**
  * of_irq_parse_raw - Low level interrupt tree parsing
  * @addr:	address specifier (start of "reg" property of the device) in be32 format
diff --git a/include/linux/of_irq.h b/include/linux/of_irq.h
index 6337ad4e5fe8..b89920c6ab55 100644
--- a/include/linux/of_irq.h
+++ b/include/linux/of_irq.h
@@ -47,6 +47,10 @@ extern int of_irq_get_byname(struct device_node *dev, const char *name);
 extern int of_irq_to_resource_table(struct device_node *dev,
 		struct resource *res, int nr_irqs);
 extern struct device_node *of_irq_find_parent(struct device_node *child);
+extern int of_irq_foreach_imap(struct device_node *np,
+			       int (*func)(void *data, const __be32 *imap,
+					   const struct of_phandle_args *parent_args),
+			       void *data);
 extern struct irq_domain *of_msi_get_domain(struct device *dev,
 					    const struct device_node *np,
 					    enum irq_domain_bus_token token);
@@ -85,6 +89,13 @@ static inline void *of_irq_find_parent(struct device_node *child)
 {
 	return NULL;
 }
+static inline int of_irq_foreach_imap(struct device_node *np,
+				      int (*func)(void *data, const __be32 *imap,
+						  const struct of_phandle_args *parent_args),
+				      void *data)
+{
+	return -EINVAL;
+}
 
 static inline struct irq_domain *of_msi_get_domain(struct device *dev,
 						   struct device_node *np,
-- 
2.50.1

[PATCH 5/6] soc: renesas: Add support for Renesas RZ/N1 GPIO Interrupt Multiplexer

[Herve Codina]

On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those
interruption lines are multiplexed by the GPIO Interrupt Multiplexer in
order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.

The GPIO interrupt multiplexer IP does nothing but select 8 GPIO
IRQ lines out of the 96 available to wire them to the GIC input lines.

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
 drivers/soc/renesas/Kconfig       |   4 +
 drivers/soc/renesas/Makefile      |   1 +
 drivers/soc/renesas/rzn1_irqmux.c | 169 ++++++++++++++++++++++++++++++
 3 files changed, 174 insertions(+)
 create mode 100644 drivers/soc/renesas/rzn1_irqmux.c

diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index fbc3b69d21a7..9e8ac33052fb 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -58,6 +58,7 @@ config ARCH_RZN1
 	select PM
 	select PM_GENERIC_DOMAINS
 	select ARM_AMBA
+	select RZN1_IRQMUX
 
 if ARM && ARCH_RENESAS
 
@@ -435,6 +436,9 @@ config PWC_RZV2M
 config RST_RCAR
 	bool "Reset Controller support for R-Car" if COMPILE_TEST
 
+config RZN1_IRQMUX
+	bool "Renesas RZ/N1 GPIO IRQ multiplexer support" if COMPILE_TEST
+
 config SYSC_RZ
 	bool "System controller for RZ SoCs" if COMPILE_TEST
 
diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
index 3bdcc6a395d5..daa932c7698d 100644
--- a/drivers/soc/renesas/Makefile
+++ b/drivers/soc/renesas/Makefile
@@ -14,4 +14,5 @@ obj-$(CONFIG_SYS_R9A09G057)	+= r9a09g057-sys.o
 # Family
 obj-$(CONFIG_PWC_RZV2M)		+= pwc-rzv2m.o
 obj-$(CONFIG_RST_RCAR)		+= rcar-rst.o
+obj-$(CONFIG_RZN1_IRQMUX)		+= rzn1_irqmux.o
 obj-$(CONFIG_SYSC_RZ)		+= rz-sysc.o
diff --git a/drivers/soc/renesas/rzn1_irqmux.c b/drivers/soc/renesas/rzn1_irqmux.c
new file mode 100644
index 000000000000..37e41c2b9104
--- /dev/null
+++ b/drivers/soc/renesas/rzn1_irqmux.c
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * RZ/N1 GPIO Interrupt Multiplexer
+ *
+ * Copyright 2025 Schneider Electric
+ * Author: Herve Codina <herve.codina@bootlin.com>
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+
+#define IRQMUX_MAX_IRQS 8
+
+static int irqmux_is_phandle_args_equal(const struct of_phandle_args *a,
+					const struct of_phandle_args *b)
+{
+	int i;
+
+	if (a->np != b->np)
+		return false;
+
+	if (a->args_count != b->args_count)
+		return false;
+
+	for (i = 0; i < a->args_count; i++) {
+		if (a->args[i] != b->args[i])
+			return false;
+	}
+
+	return true;
+}
+
+static int irqmux_find_interrupt_index(struct device *dev, struct device_node *np,
+				       const struct of_phandle_args *expected_irq)
+{
+	struct of_phandle_args out_irq;
+	bool is_equal;
+	int ret;
+	int i;
+
+	for (i = 0; i < IRQMUX_MAX_IRQS; i++) {
+		ret = of_irq_parse_one(np, i, &out_irq);
+		if (ret)
+			return ret;
+
+		is_equal = irqmux_is_phandle_args_equal(expected_irq, &out_irq);
+		of_node_put(out_irq.np);
+		if (is_equal)
+			return i;
+	}
+
+	return -ENOENT;
+}
+
+struct irqmux_cb_data {
+	struct device_node *np;
+	struct device *dev;
+	u32 __iomem *regs;
+};
+
+static int irqmux_imap_cb(void *data, const __be32 *imap,
+			  const struct of_phandle_args *parent_args)
+{
+	struct irqmux_cb_data *priv = data;
+	u32 src_hwirq;
+	int index;
+
+	/*
+	 * The child #address-cells is 0. Already checked in irqmux_setup().
+	 * The first value in imap is the src_hwirq
+	 */
+	src_hwirq = be32_to_cpu(*imap);
+
+	/*
+	 * Get the index in our interrupt array that matches the parent in the
+	 * interrupt-map
+	 */
+	index = irqmux_find_interrupt_index(priv->dev, priv->np, parent_args);
+	if (index < 0)
+		return dev_err_probe(priv->dev, index, "output interrupt not found\n");
+
+	dev_info(priv->dev, "interrupt %u mapped to output interrupt[%u]\n",
+		 src_hwirq, index);
+
+	/*
+	 * Our interrupt array items matches 1:1 the interrupt lines that could
+	 * be configured by registers (same order, same number).
+	 * Configure the related register with the src hwirq retrieved from the
+	 * interrupt-map.
+	 */
+	writel(src_hwirq, priv->regs + index);
+
+	return 0;
+}
+
+static int irqmux_setup(struct device *dev, struct device_node *np, u32 __iomem *regs)
+{
+	struct irqmux_cb_data cb_data;
+	u32 tmp;
+	int ret;
+
+	/* We support only #interrupt-cells = <1> and #address-cells = <0> */
+	ret = of_property_read_u32(np, "#interrupt-cells", &tmp);
+	if (ret)
+		return ret;
+	if (tmp != 1)
+		return -EINVAL;
+
+	ret = of_property_read_u32(np, "#address-cells", &tmp);
+	if (ret)
+		return ret;
+	if (tmp != 0)
+		return -EINVAL;
+
+	cb_data.dev = dev;
+	cb_data.regs = regs;
+	cb_data.np = np;
+	return of_irq_foreach_imap(np, irqmux_imap_cb, &cb_data);
+}
+
+static int irqmux_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	u32 __iomem *regs;
+	int nr_irqs;
+	int ret;
+
+	regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(regs))
+		return PTR_ERR(regs);
+
+	nr_irqs = of_irq_count(np);
+	if (nr_irqs < 0)
+		return nr_irqs;
+
+	if (nr_irqs > IRQMUX_MAX_IRQS) {
+		dev_err(dev, "too many output interrupts\n");
+		return -ENOENT;
+	}
+
+	ret = irqmux_setup(dev, np, regs);
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to setup mux\n");
+
+	return 0;
+}
+
+static const struct of_device_id irqmux_of_match[] = {
+	{ .compatible = "renesas,rzn1-gpioirqmux", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, irq_mux_of_match);
+
+static struct platform_driver irqmux_driver = {
+	.probe = irqmux_probe,
+	.driver = {
+		.name = "rzn1_irqmux",
+		.of_match_table = irqmux_of_match,
+	},
+};
+module_platform_driver(irqmux_driver);
+
+MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
+MODULE_DESCRIPTION("Renesas RZ/N1 GPIO IRQ Multiplexer Driver");
+MODULE_LICENSE("GPL");
-- 
2.50.1

[PATCH 6/6] ARM: dts: r9a06g032: Add support for GPIO interrupts

[Herve Codina]

In the RZ/N1 SoC, the GPIO interrupts are multiplexed using the GPIO
Interrupt Multiplexer.

Add the multiplexer node and connect GPIO interrupt lines to the
multiplexer.

The interrupt-map available in the multiplexer node has to be updated in
dts files depending on the GPIO usage. Indeed, the usage of an interrupt
for a GPIO is board dependent.

Up to 8 GPIOs can be used as an interrupt line (one per multiplexer
output interrupt).

Signed-off-by: Herve Codina <herve.codina@bootlin.com>
---
 arch/arm/boot/dts/renesas/r9a06g032.dtsi | 45 ++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
index 7f71c01af409..0e2e0fe92cd3 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi
+++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi
@@ -535,6 +535,14 @@ gpio0a: gpio@0 {
 				#gpio-cells = <2>;
 				snps,nr-gpios = <32>;
 				reg = <0>;
+
+				interrupt-controller;
+				interrupt-parent = <&gpioirqmux>;
+				interrupts = < 0  1  2  3  4  5  6  7
+					       8  9 10 11 12 13 14 15
+					      16 17 18 19 20 21 22 23
+					      24 25 26 27 28 29 30 31 >;
+				#interrupt-cells = <2>;
 			};
 
 			/* GPIO0b[0..1]   connected to pins GPIO1..2   */
@@ -579,6 +587,14 @@ gpio1a: gpio@0 {
 				#gpio-cells = <2>;
 				snps,nr-gpios = <32>;
 				reg = <0>;
+
+				interrupt-controller;
+				interrupt-parent = <&gpioirqmux>;
+				interrupts = < 32 33 34 35 36 37 38 39
+					       40 41 42 43 44 45 46 47
+					       48 49 50 51 52 53 54 55
+					       56 57 58 59 60 61 62 63 >;
+				#interrupt-cells = <2>;
 			};
 
 			/* GPIO1b[0..1]   connected to pins GPIO55..56 */
@@ -613,6 +629,14 @@ gpio2a: gpio@0 {
 				#gpio-cells = <2>;
 				snps,nr-gpios = <32>;
 				reg = <0>;
+
+				interrupt-controller;
+				interrupt-parent = <&gpioirqmux>;
+				interrupts = < 64 65 66 67 68 69 70 71
+					       72 73 74 75 76 77 78 79
+					       80 81 82 83 84 85 86 87
+					       88 89 90 91 92 93 94 95 >;
+				#interrupt-cells = <2>;
 			};
 
 			/* GPIO2b[0..9] connected to pins GPIO160..169 */
@@ -626,6 +650,27 @@ gpio2b: gpio@1 {
 			};
 		};
 
+		gpioirqmux: interrupt-controller@51000480 {
+			compatible = "renesas,r9a06g032-gpioirqmux", "renesas,rzn1-gpioirqmux";
+			reg = <0x51000480 0x20>;
+			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <1>;
+			#address-cells = <0>;
+			interrupt-map-mask = <0x7f>;
+
+			/* interrupt-map has to be updated according to GPIO usage */
+			interrupt-map = <0 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+
+			status = "disabled";
+		};
+
 		can0: can@52104000 {
 			compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000";
 			reg = <0x52104000 0x800>;
-- 
2.50.1

Re: [PATCH 0/6] gpio: renesas: Add support for GPIO and related interrupts in RZ/N1 SoC

[Rob Herring (Arm)]

On Fri, 25 Jul 2025 17:26:09 +0200, Herve Codina wrote:
> Hi,
> 
> This series adds support for GPIO and GPIO IRQ mux available in the
> RZ/N1 SoCs.
> 
> The first two patches of the series add support for GPIO (binding update
> and device-tree description).
> 
> Other patches are related to GPIO interrupts and GPIO IRQ multiplexer.
> 
> In the RZ/N1 SoCs, GPIO interrupts are wired to a GPIO IRQ multiplexer.
> 
> This multiplexer does nothing but select 8 GPIO IRQ lines out of the 96
> available to wire them to the GIC input lines.
> 
> One upstreaming attempt have been done previously by Phil Edworthy [1]
> but the series has never been applied.
> 
> Based on my understanding, I have fully reworked the driver proposed by
> Phil and removed the IRQ domain. Indeed, the device doesn't handle
> interrupts. It just routes signals.
> 
> Also, as an interrupt-map property is used, the driver cannot be
> involved as an interrupt controller itself. It is a nexus node.
> 
> With that in mind, patch 3 is related to the binding, patch 4 introduces
> an helper to parse the interrupt-map property. This parsing is needed by
> the driver. Indeed, the lines routing is defined by the interrupt-map
> property and the driver needs to set registers to apply this routing.
> 
> The last two patches are the driver itself and the RZ/N1 device-tree
> description update to have the support for the GPIO interrupts.
> 
> [1] https://lore.kernel.org/all/20190219155511.28507-1-phil.edworthy@renesas.com/
> 
> Best regards,
> Hervé
> 
> Herve Codina (6):
>   dt-bindings: gpio: snps,dw-apb: Add support for Renesas RZ/N1
>   ARM: dts: r9a06g032: Add GPIO controllers
>   dt-bindings: soc: renesas: Add the Renesas RZ/N1 GPIO Interrupt
>     Multiplexer
>   of/irq: Introduce of_irq_foreach_imap
>   soc: renesas: Add support for Renesas RZ/N1 GPIO Interrupt Multiplexer
>   ARM: dts: r9a06g032: Add support for GPIO interrupts
> 
>  .../bindings/gpio/snps,dw-apb-gpio.yaml       |   8 +-
>  .../soc/renesas/renesas,rzn1-gpioirqmux.yaml  |  99 ++++++++++
>  arch/arm/boot/dts/renesas/r9a06g032.dtsi      | 172 ++++++++++++++++++
>  drivers/of/irq.c                              |  70 +++++++
>  drivers/soc/renesas/Kconfig                   |   4 +
>  drivers/soc/renesas/Makefile                  |   1 +
>  drivers/soc/renesas/rzn1_irqmux.c             | 169 +++++++++++++++++
>  include/linux/of_irq.h                        |  11 ++
>  8 files changed, 533 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/soc/renesas/renesas,rzn1-gpioirqmux.yaml
>  create mode 100644 drivers/soc/renesas/rzn1_irqmux.c
> 
> --
> 2.50.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: attempting to guess base-commit...
 Base: tags/v6.16-rc3-23-g03a28dc39838 (exact match)

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm/boot/dts/renesas/' for 20250725152618.32886-1-herve.codina@bootlin.com:

arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dtb: gpio@5000b000 (renesas,r9a06g032-gpio): 'gpio@0', 'gpio@1' do not match any of the regexes: '^gpio-(port|controller)@[0-9a-f]+$', '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dtb: gpio@5000c000 (renesas,r9a06g032-gpio): 'gpio@0', 'gpio@1' do not match any of the regexes: '^gpio-(port|controller)@[0-9a-f]+$', '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dtb: gpio@5000d000 (renesas,r9a06g032-gpio): 'gpio@0', 'gpio@1' do not match any of the regexes: '^gpio-(port|controller)@[0-9a-f]+$', '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dtb: gpio@5000b000 (renesas,r9a06g032-gpio): 'gpio@0', 'gpio@1' do not match any of the regexes: '^gpio-(port|controller)@[0-9a-f]+$', '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dtb: gpio@5000c000 (renesas,r9a06g032-gpio): 'gpio@0', 'gpio@1' do not match any of the regexes: '^gpio-(port|controller)@[0-9a-f]+$', '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dtb: gpio@5000d000 (renesas,r9a06g032-gpio): 'gpio@0', 'gpio@1' do not match any of the regexes: '^gpio-(port|controller)@[0-9a-f]+$', '^pinctrl-[0-9]+$'
	from schema $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#

Re: [PATCH 0/6] gpio: renesas: Add support for GPIO and related interrupts in RZ/N1 SoC

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 2409 bytes --]

Hi Hervé,

> This series adds support for GPIO and GPIO IRQ mux available in the
> RZ/N1 SoCs.

Yes, way cool! Very happy to see this upstreaming effort!

> The first two patches of the series add support for GPIO (binding update
> and device-tree description).

So, I started simple and used the first two patches to enable LEDs on
pins 92 and 93 on my board. I added this on top of patch 1+2:

diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
index 3258b2e27434..4790ffad578f 100644
--- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
+++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
@@ -185,6 +185,12 @@ fixed-link {
 	};
 };
 
+&gpio1 {
+	pinctrl-0 = <&pins_gpio1>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &i2c2 {
 	pinctrl-0 = <&pins_i2c2>;
 	pinctrl-names = "default";
@@ -256,6 +262,11 @@ pins_cpld: pins-cpld {
 			 <RZN1_PINMUX(122, RZN1_FUNC_USB)>;
 	};
 
+	pins_gpio1: pins-gpio1 {
+		pinmux = <RZN1_PINMUX(92, RZN1_FUNC_GPIO)>,	/* GPIO1B[23] */
+			 <RZN1_PINMUX(93, RZN1_FUNC_GPIO)>;	/* GPIO1B[24] */
+	};
+
 	pins_eth3: pins_eth3 {
 		pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
 			 <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>

to my board dts. The controller gets probed but I can't control the
LEDs. Neither with exported GPIOs (via sysfs) nor with a dedicated LED
node. Am I missing something obvious? The LEDs are attached to PL_GPIO92
and PL_GPIO93 which are mapped to GPIO1b[23] and GPIO1b[24]. That seems
to be in accordance with the datasheet. I hope I just overlooked
something simple. Some outputs, first /sys/kernel/debug/gpio:

	...
	gpiochip1: GPIOs 552-583, parent: platform/5000c000.gpio, 5000c000.gpio:

	gpiochip2: GPIOs 584-615, parent: platform/5000c000.gpio, 5000c000.gpio:
	 gpio-608 (                    |sysfs               ) out hi 

And /sys/kernel/debug/pinctrl/40067000.pinctrl/pinmux-pins:

	Pinmux settings per pin
	Format: pin (name): mux_owner gpio_owner hog?
	...
	pin 92 (pl_gpio92): 5000c000.gpio (GPIO UNCLAIMED) function pins-gpio1 group pins-gpio1
	pin 93 (pl_gpio93): 5000c000.gpio (GPIO UNCLAIMED) function pins-gpio1 group pins-gpio1

I wonder about the "(GPIO UNCLAIMED)" a little? How do you use it on
your board?

Thanks and happy hacking,

   Wolfram


[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH 1/6] dt-bindings: gpio: snps,dw-apb: Add support for Renesas RZ/N1

[Rob Herring]

On Fri, Jul 25, 2025 at 05:26:10PM +0200, Herve Codina wrote:
> The RZ/N1 SoCs uses the Synopsys DesignWare IP to handle GPIO blocks.
> 
> Add RZ/N1 SoC and family compatible strings.

Why? Yes, that's policy, but so far we avoided it on this IP. Perhaps 
because it is simple enough. So what's different here?

> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
>  .../devicetree/bindings/gpio/snps,dw-apb-gpio.yaml        | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml
> index ab2afc0e4153..ceb71b5ac688 100644
> --- a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml
> +++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml
> @@ -20,7 +20,13 @@ properties:
>      pattern: "^gpio@[0-9a-f]+$"
>  
>    compatible:
> -    const: snps,dw-apb-gpio
> +    oneOf:
> +      - const: snps,dw-apb-gpio
> +      - items:
> +          - enum:
> +              - renesas,r9a06g032-gpio
> +          - const: renesas,rzn1-gpio
> +          - const: snps,dw-apb-gpio
>  
>    "#address-cells":
>      const: 1
> -- 
> 2.50.1
> 

Re: [PATCH 5/6] soc: renesas: Add support for Renesas RZ/N1 GPIO Interrupt Multiplexer

[Rob Herring]

On Fri, Jul 25, 2025 at 05:26:14PM +0200, Herve Codina wrote:
> On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those
> interruption lines are multiplexed by the GPIO Interrupt Multiplexer in
> order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.
> 
> The GPIO interrupt multiplexer IP does nothing but select 8 GPIO
> IRQ lines out of the 96 available to wire them to the GIC input lines.
> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
>  drivers/soc/renesas/Kconfig       |   4 +
>  drivers/soc/renesas/Makefile      |   1 +
>  drivers/soc/renesas/rzn1_irqmux.c | 169 ++++++++++++++++++++++++++++++
>  3 files changed, 174 insertions(+)
>  create mode 100644 drivers/soc/renesas/rzn1_irqmux.c
> 
> diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
> index fbc3b69d21a7..9e8ac33052fb 100644
> --- a/drivers/soc/renesas/Kconfig
> +++ b/drivers/soc/renesas/Kconfig
> @@ -58,6 +58,7 @@ config ARCH_RZN1
>  	select PM
>  	select PM_GENERIC_DOMAINS
>  	select ARM_AMBA
> +	select RZN1_IRQMUX
>  
>  if ARM && ARCH_RENESAS
>  
> @@ -435,6 +436,9 @@ config PWC_RZV2M
>  config RST_RCAR
>  	bool "Reset Controller support for R-Car" if COMPILE_TEST
>  
> +config RZN1_IRQMUX
> +	bool "Renesas RZ/N1 GPIO IRQ multiplexer support" if COMPILE_TEST
> +
>  config SYSC_RZ
>  	bool "System controller for RZ SoCs" if COMPILE_TEST
>  
> diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
> index 3bdcc6a395d5..daa932c7698d 100644
> --- a/drivers/soc/renesas/Makefile
> +++ b/drivers/soc/renesas/Makefile
> @@ -14,4 +14,5 @@ obj-$(CONFIG_SYS_R9A09G057)	+= r9a09g057-sys.o
>  # Family
>  obj-$(CONFIG_PWC_RZV2M)		+= pwc-rzv2m.o
>  obj-$(CONFIG_RST_RCAR)		+= rcar-rst.o
> +obj-$(CONFIG_RZN1_IRQMUX)		+= rzn1_irqmux.o
>  obj-$(CONFIG_SYSC_RZ)		+= rz-sysc.o
> diff --git a/drivers/soc/renesas/rzn1_irqmux.c b/drivers/soc/renesas/rzn1_irqmux.c
> new file mode 100644
> index 000000000000..37e41c2b9104
> --- /dev/null
> +++ b/drivers/soc/renesas/rzn1_irqmux.c
> @@ -0,0 +1,169 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * RZ/N1 GPIO Interrupt Multiplexer
> + *
> + * Copyright 2025 Schneider Electric
> + * Author: Herve Codina <herve.codina@bootlin.com>
> + */
> +
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +
> +#define IRQMUX_MAX_IRQS 8
> +
> +static int irqmux_is_phandle_args_equal(const struct of_phandle_args *a,
> +					const struct of_phandle_args *b)
> +{
> +	int i;
> +
> +	if (a->np != b->np)
> +		return false;
> +
> +	if (a->args_count != b->args_count)
> +		return false;
> +
> +	for (i = 0; i < a->args_count; i++) {
> +		if (a->args[i] != b->args[i])
> +			return false;
> +	}
> +
> +	return true;
> +}
> +
> +static int irqmux_find_interrupt_index(struct device *dev, struct device_node *np,
> +				       const struct of_phandle_args *expected_irq)
> +{
> +	struct of_phandle_args out_irq;
> +	bool is_equal;
> +	int ret;
> +	int i;
> +
> +	for (i = 0; i < IRQMUX_MAX_IRQS; i++) {
> +		ret = of_irq_parse_one(np, i, &out_irq);

I don't really want more users of this... More below.

> +		if (ret)
> +			return ret;
> +
> +		is_equal = irqmux_is_phandle_args_equal(expected_irq, &out_irq);
> +		of_node_put(out_irq.np);
> +		if (is_equal)
> +			return i;
> +	}
> +
> +	return -ENOENT;
> +}
> +
> +struct irqmux_cb_data {
> +	struct device_node *np;
> +	struct device *dev;
> +	u32 __iomem *regs;
> +};
> +
> +static int irqmux_imap_cb(void *data, const __be32 *imap,
> +			  const struct of_phandle_args *parent_args)
> +{
> +	struct irqmux_cb_data *priv = data;
> +	u32 src_hwirq;
> +	int index;
> +
> +	/*
> +	 * The child #address-cells is 0. Already checked in irqmux_setup().
> +	 * The first value in imap is the src_hwirq
> +	 */
> +	src_hwirq = be32_to_cpu(*imap);

The iterator should take care of the endianness conversion.

> +
> +	/*
> +	 * Get the index in our interrupt array that matches the parent in the
> +	 * interrupt-map
> +	 */
> +	index = irqmux_find_interrupt_index(priv->dev, priv->np, parent_args);
> +	if (index < 0)
> +		return dev_err_probe(priv->dev, index, "output interrupt not found\n");
> +
> +	dev_info(priv->dev, "interrupt %u mapped to output interrupt[%u]\n",
> +		 src_hwirq, index);

Do you even need "interrupts"? Just make the "interrupt-map" index 
important and correspond to the hw index. That would greatly simplify 
all this.

> +
> +	/*
> +	 * Our interrupt array items matches 1:1 the interrupt lines that could
> +	 * be configured by registers (same order, same number).
> +	 * Configure the related register with the src hwirq retrieved from the
> +	 * interrupt-map.
> +	 */
> +	writel(src_hwirq, priv->regs + index);
> +
> +	return 0;
> +}

Re: [PATCH 4/6] of/irq: Introduce of_irq_foreach_imap

[Rob Herring]

On Fri, Jul 25, 2025 at 05:26:13PM +0200, Herve Codina wrote:
> of_irq_foreach_imap is an iterator designed to help a driver to parse
> an interrupt-map property.
> 
> Indeed some drivers need to know details about the interrupt mapping
> described in the device-tree in order to set internal registers
> accordingly.

I would like to see some existing user converted to make sure it works 
for other cases.

> 
> Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> ---
>  drivers/of/irq.c       | 70 ++++++++++++++++++++++++++++++++++++++++++
>  include/linux/of_irq.h | 11 +++++++
>  2 files changed, 81 insertions(+)
> 
> diff --git a/drivers/of/irq.c b/drivers/of/irq.c
> index f8ad79b9b1c9..863b31eb3c1a 100644
> --- a/drivers/of/irq.c
> +++ b/drivers/of/irq.c
> @@ -157,6 +157,76 @@ const __be32 *of_irq_parse_imap_parent(const __be32 *imap, int len, struct of_ph
>  	return imap;
>  }
>  
> +/**
> + * of_irq_foreach_imap - Iterate through interrupt-map items
> + * @np: device node where interrupt-map is available
> + * @func: function called on each interrupt-map items
> + * @data: data passe to @func
> + *
> + * This function iterates through interrupt-map items and calls @func on each
> + * item. The parent interrupt described in the interrupt-map item is parsed
> + * and passed to @func using a pointer to a struct of_phandle_args.
> + * Also the imap raw value is passed in order to allow @func to look at other
> + * values of the interrupt-map (child unit address and child interrupt
> + * specificer)
> + *
> + * If @func returns an error, the iteration stops and this error is returned.
> + */
> +int of_irq_foreach_imap(struct device_node *np,
> +			int (*func)(void *data,
> +				    const __be32 *imap,
> +				    const struct of_phandle_args *parent_args),
> +			void *data)

The func callback is a departure from other DT iterators. Look at the 
'ranges' iterator which keeps the state on each iteration.

Rob

Re: [PATCH 0/6] gpio: renesas: Add support for GPIO and related interrupts in RZ/N1 SoC

[Herve Codina]

Hi Wolfram,

On Sun, 27 Jul 2025 13:01:35 +0200
Wolfram Sang <wsa+renesas@sang-engineering.com> wrote:

> Hi Hervé,
> 
> > This series adds support for GPIO and GPIO IRQ mux available in the
> > RZ/N1 SoCs.  
> 
> Yes, way cool! Very happy to see this upstreaming effort!
> 
> > The first two patches of the series add support for GPIO (binding update
> > and device-tree description).  
> 
> So, I started simple and used the first two patches to enable LEDs on
> pins 92 and 93 on my board. I added this on top of patch 1+2:
> 
> diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
> index 3258b2e27434..4790ffad578f 100644
> --- a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
> +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-db.dts
> @@ -185,6 +185,12 @@ fixed-link {
>  	};
>  };
>  
> +&gpio1 {
> +	pinctrl-0 = <&pins_gpio1>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
>  &i2c2 {
>  	pinctrl-0 = <&pins_i2c2>;
>  	pinctrl-names = "default";
> @@ -256,6 +262,11 @@ pins_cpld: pins-cpld {
>  			 <RZN1_PINMUX(122, RZN1_FUNC_USB)>;
>  	};
>  
> +	pins_gpio1: pins-gpio1 {
> +		pinmux = <RZN1_PINMUX(92, RZN1_FUNC_GPIO)>,	/* GPIO1B[23] */
> +			 <RZN1_PINMUX(93, RZN1_FUNC_GPIO)>;	/* GPIO1B[24] */
> +	};
> +
>  	pins_eth3: pins_eth3 {
>  		pinmux = <RZN1_PINMUX(36, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
>  			 <RZN1_PINMUX(37, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>
> 
> to my board dts. The controller gets probed but I can't control the
> LEDs. Neither with exported GPIOs (via sysfs) nor with a dedicated LED
> node. Am I missing something obvious? The LEDs are attached to PL_GPIO92
> and PL_GPIO93 which are mapped to GPIO1b[23] and GPIO1b[24]. That seems
> to be in accordance with the datasheet. I hope I just overlooked
> something simple. Some outputs, first /sys/kernel/debug/gpio:
> 
> 	...
> 	gpiochip1: GPIOs 552-583, parent: platform/5000c000.gpio, 5000c000.gpio:
> 
> 	gpiochip2: GPIOs 584-615, parent: platform/5000c000.gpio, 5000c000.gpio:
> 	 gpio-608 (                    |sysfs               ) out hi 
> 
> And /sys/kernel/debug/pinctrl/40067000.pinctrl/pinmux-pins:
> 
> 	Pinmux settings per pin
> 	Format: pin (name): mux_owner gpio_owner hog?
> 	...
> 	pin 92 (pl_gpio92): 5000c000.gpio (GPIO UNCLAIMED) function pins-gpio1 group pins-gpio1
> 	pin 93 (pl_gpio93): 5000c000.gpio (GPIO UNCLAIMED) function pins-gpio1 group pins-gpio1
> 
> I wonder about the "(GPIO UNCLAIMED)" a little? How do you use it on
> your board?
> 

Strange, I have a LED working on my side.

My LED is connected to gpio0b[9] (GPIO17).

I just used:
--- 8< ---
	gpio_leds {
		compatible = "gpio-leds";

		led_1g: led-0 {
			label = "led_1g";
			gpios = <&gpio0b 9 GPIO_ACTIVE_HIGH>;
		};
	};

	&gpio0 {
		pinctrl-0 = <&pins_gpio0>;
		pinctrl-names = "default";
		status = "okay";
	};

	&pinctrl{
		/*
		 * I have other pins used as GPIOs but my led is :
		 *    RZN1_PINMUX(17, RZN1_FUNC_GPIO)
		 */

		pins_gpio0: pins_gpio0 {
			pinmux = <
				RZN1_PINMUX(13, RZN1_FUNC_GPIO)	/* GPIO0B[7] */
				RZN1_PINMUX(14, RZN1_FUNC_GPIO)	/* GPIO0B[8] */
				RZN1_PINMUX(15, RZN1_FUNC_GPIO)	/* GPIO0A[6] */
				RZN1_PINMUX(16, RZN1_FUNC_GPIO)	/* GPIO0A[7] */
				RZN1_PINMUX(17, RZN1_FUNC_GPIO)	/* GPIO0B[9] */
				RZN1_PINMUX(18, RZN1_FUNC_GPIO)	/* GPIO0B[10] */
				RZN1_PINMUX(22, RZN1_FUNC_GPIO)	/* GPIO0A[9] */
				RZN1_PINMUX(23, RZN1_FUNC_GPIO)	/* GPIO0B[13] */
			>;
			drive-strength = <6>;
			bias-disable;
		pins_gpio0_pullup {
			pinmux = <
				RZN1_PINMUX(25, RZN1_FUNC_GPIO)	/* GPIO0B[14] - A70CI_EN_N */
				RZN1_PINMUX(26, RZN1_FUNC_GPIO)	/* GPIO0B[15] - A71CH_EN_N */
				RZN1_PINMUX(27, RZN1_FUNC_GPIO)	/* GPIO0A[11] - TRUST_M_EN_N */
				RZN1_PINMUX(28, RZN1_FUNC_GPIO)	/* GPIO0A[12] - TRUST_X_EN_N */
				RZN1_PINMUX(32, RZN1_FUNC_GPIO)	/* GPIO0B[19] - STMA100_EN_N*/
			>;
			drive-strength = <6>;
			bias-pull-up;
		};

	};
--- 8< ---

Of course with:
  CONFIG_GPIO_DWAPB=y
  CONFIG_LEDS_CLASS=y
  CONFIG_LEDS_GPIO=y

My led is accessible from the user-space without any issue:
  echo 255 > /sys/class/leds/led_1g/brightness

I have checked /sys/kernel/debug/pinctrl/40067000.pinctrl/pinmux-pins and
I have also the "(GPIO UNCLAIMED)":
	...
	pin 12 (pl_gpio12): (MUX UNCLAIMED) (GPIO UNCLAIMED)
	pin 13 (pl_gpio13): 5000b000.gpio (GPIO UNCLAIMED) function pins_gpio0 group pins_gpio0
	pin 14 (pl_gpio14): 5000b000.gpio (GPIO UNCLAIMED) function pins_gpio0 group pins_gpio0
	pin 15 (pl_gpio15): 5000b000.gpio (GPIO UNCLAIMED) function pins_gpio0 group pins_gpio0
	pin 16 (pl_gpio16): 5000b000.gpio (GPIO UNCLAIMED) function pins_gpio0 group pins_gpio0
	pin 17 (pl_gpio17): 5000b000.gpio (GPIO UNCLAIMED) function pins_gpio0 group pins_gpio0
	pin 18 (pl_gpio18): 5000b000.gpio (GPIO UNCLAIMED) function pins_gpio0 group pins_gpio0
	pin 19 (pl_gpio19): (MUX UNCLAIMED) (GPIO UNCLAIMED)
	pin 20 (pl_gpio20): (MUX UNCLAIMED) (GPIO UNCLAIMED)
	pin 21 (pl_gpio21): (MUX UNCLAIMED) (GPIO UNCLAIMED)
	pin 22 (pl_gpio22): 5000b000.gpio (GPIO UNCLAIMED) function pins_gpio0 group pins_gpio0
	pin 23 (pl_gpio23): 5000b000.gpio (GPIO UNCLAIMED) function pins_gpio0 group pins_gpio0
	pin 24 (pl_gpio24): (MUX UNCLAIMED) (GPIO UNCLAIMED)
	pin 25 (pl_gpio25): 5000b000.gpio (GPIO UNCLAIMED) function pins_gpio0 group pins_gpio0_pullup
	pin 26 (pl_gpio26): 5000b000.gpio (GPIO UNCLAIMED) function pins_gpio0 group pins_gpio0_pullup
	pin 27 (pl_gpio27): 5000b000.gpio (GPIO UNCLAIMED) function pins_gpio0 group pins_gpio0_pullup
	pin 28 (pl_gpio28): 5000b000.gpio (GPIO UNCLAIMED) function pins_gpio0 group pins_gpio0_pullup
	pin 29 (pl_gpio29): (MUX UNCLAIMED) (GPIO UNCLAIMED)
	pin 30 (pl_gpio30): (MUX UNCLAIMED) (GPIO UNCLAIMED)
	pin 31 (pl_gpio31): (MUX UNCLAIMED) (GPIO UNCLAIMED)
	pin 32 (pl_gpio32): 5000b000.gpio (GPIO UNCLAIMED) function pins_gpio0 group pins_gpio0_pullup
	pin 33 (pl_gpio33): (MUX UNCLAIMED) (GPIO UNCLAIMED)
	...

When you described the LED on your side, did you reference the GPIO using &gpio1b
for instance gpios = <&gpio1b 23 GPIO_ACTIVE_HIGH>;

For GPIO accesses from user space I used gpioget/gpioset tools from libgpiod
without any issues to read/write a GPIO.

Best regards,
Hervé

Re: [PATCH 1/6] dt-bindings: gpio: snps,dw-apb: Add support for Renesas RZ/N1

[Herve Codina]

Hi Rob,

On Tue, 29 Jul 2025 13:11:51 -0500
Rob Herring <robh@kernel.org> wrote:

> On Fri, Jul 25, 2025 at 05:26:10PM +0200, Herve Codina wrote:
> > The RZ/N1 SoCs uses the Synopsys DesignWare IP to handle GPIO blocks.
> > 
> > Add RZ/N1 SoC and family compatible strings.  
> 
> Why? Yes, that's policy, but so far we avoided it on this IP. Perhaps 
> because it is simple enough. So what's different here?

I've just followed Renesas policy.

Nothing other than this policy justifies the change and so, I can remove
the Renesas compatible strings. In other words, I can simply remove this
patch.

Best regards,
Hervé

Re: [PATCH 4/6] of/irq: Introduce of_irq_foreach_imap

[Herve Codina]

Hi Rob,

On Tue, 29 Jul 2025 14:51:51 -0500
Rob Herring <robh@kernel.org> wrote:

> On Fri, Jul 25, 2025 at 05:26:13PM +0200, Herve Codina wrote:
> > of_irq_foreach_imap is an iterator designed to help a driver to parse
> > an interrupt-map property.
> > 
> > Indeed some drivers need to know details about the interrupt mapping
> > described in the device-tree in order to set internal registers
> > accordingly.  
> 
> I would like to see some existing user converted to make sure it works 
> for other cases.

I will see what I can do for the next iteration.
Maybe I will propose a unit test for this new API.

> 
> > 
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> > ---
> >  drivers/of/irq.c       | 70 ++++++++++++++++++++++++++++++++++++++++++
> >  include/linux/of_irq.h | 11 +++++++
> >  2 files changed, 81 insertions(+)
> > 
> > diff --git a/drivers/of/irq.c b/drivers/of/irq.c
> > index f8ad79b9b1c9..863b31eb3c1a 100644
> > --- a/drivers/of/irq.c
> > +++ b/drivers/of/irq.c
> > @@ -157,6 +157,76 @@ const __be32 *of_irq_parse_imap_parent(const __be32 *imap, int len, struct of_ph
> >  	return imap;
> >  }
> >  
> > +/**
> > + * of_irq_foreach_imap - Iterate through interrupt-map items
> > + * @np: device node where interrupt-map is available
> > + * @func: function called on each interrupt-map items
> > + * @data: data passe to @func
> > + *
> > + * This function iterates through interrupt-map items and calls @func on each
> > + * item. The parent interrupt described in the interrupt-map item is parsed
> > + * and passed to @func using a pointer to a struct of_phandle_args.
> > + * Also the imap raw value is passed in order to allow @func to look at other
> > + * values of the interrupt-map (child unit address and child interrupt
> > + * specificer)
> > + *
> > + * If @func returns an error, the iteration stops and this error is returned.
> > + */
> > +int of_irq_foreach_imap(struct device_node *np,
> > +			int (*func)(void *data,
> > +				    const __be32 *imap,
> > +				    const struct of_phandle_args *parent_args),
> > +			void *data)  
> 
> The func callback is a departure from other DT iterators. Look at the 
> 'ranges' iterator which keeps the state on each iteration.
> 

I see, I will propose a reworked version in the next iteration to have
something similar to ranges:
  - of_irq_imap_parser_init()
  - for_each_of_range() with something like
       for (; of_irq_imap_parser_one(parser, imap);)
  - of_irq_imap_parser_one()
  - of_irq_imap_parser_exit(): Not sure, will see if I need to release something

Best regards,
Hervé

Re: [PATCH 5/6] soc: renesas: Add support for Renesas RZ/N1 GPIO Interrupt Multiplexer

[Herve Codina]

Hi Rob,

On Tue, 29 Jul 2025 14:51:37 -0500
Rob Herring <robh@kernel.org> wrote:

> On Fri, Jul 25, 2025 at 05:26:14PM +0200, Herve Codina wrote:
> > On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those
> > interruption lines are multiplexed by the GPIO Interrupt Multiplexer in
> > order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.
> > 
> > The GPIO interrupt multiplexer IP does nothing but select 8 GPIO
> > IRQ lines out of the 96 available to wire them to the GIC input lines.
> > 
> > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> > ---
> >  drivers/soc/renesas/Kconfig       |   4 +
> >  drivers/soc/renesas/Makefile      |   1 +
> >  drivers/soc/renesas/rzn1_irqmux.c | 169 ++++++++++++++++++++++++++++++
> >  3 files changed, 174 insertions(+)
> >  create mode 100644 drivers/soc/renesas/rzn1_irqmux.c
> > 
> > diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
> > index fbc3b69d21a7..9e8ac33052fb 100644
> > --- a/drivers/soc/renesas/Kconfig
> > +++ b/drivers/soc/renesas/Kconfig
> > @@ -58,6 +58,7 @@ config ARCH_RZN1
> >  	select PM
> >  	select PM_GENERIC_DOMAINS
> >  	select ARM_AMBA
> > +	select RZN1_IRQMUX
> >  
> >  if ARM && ARCH_RENESAS
> >  
> > @@ -435,6 +436,9 @@ config PWC_RZV2M
> >  config RST_RCAR
> >  	bool "Reset Controller support for R-Car" if COMPILE_TEST
> >  
> > +config RZN1_IRQMUX
> > +	bool "Renesas RZ/N1 GPIO IRQ multiplexer support" if COMPILE_TEST
> > +
> >  config SYSC_RZ
> >  	bool "System controller for RZ SoCs" if COMPILE_TEST
> >  
> > diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
> > index 3bdcc6a395d5..daa932c7698d 100644
> > --- a/drivers/soc/renesas/Makefile
> > +++ b/drivers/soc/renesas/Makefile
> > @@ -14,4 +14,5 @@ obj-$(CONFIG_SYS_R9A09G057)	+= r9a09g057-sys.o
> >  # Family
> >  obj-$(CONFIG_PWC_RZV2M)		+= pwc-rzv2m.o
> >  obj-$(CONFIG_RST_RCAR)		+= rcar-rst.o
> > +obj-$(CONFIG_RZN1_IRQMUX)		+= rzn1_irqmux.o
> >  obj-$(CONFIG_SYSC_RZ)		+= rz-sysc.o
> > diff --git a/drivers/soc/renesas/rzn1_irqmux.c b/drivers/soc/renesas/rzn1_irqmux.c
> > new file mode 100644
> > index 000000000000..37e41c2b9104
> > --- /dev/null
> > +++ b/drivers/soc/renesas/rzn1_irqmux.c
> > @@ -0,0 +1,169 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * RZ/N1 GPIO Interrupt Multiplexer
> > + *
> > + * Copyright 2025 Schneider Electric
> > + * Author: Herve Codina <herve.codina@bootlin.com>
> > + */
> > +
> > +#include <linux/mod_devicetable.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/platform_device.h>
> > +
> > +#define IRQMUX_MAX_IRQS 8
> > +
> > +static int irqmux_is_phandle_args_equal(const struct of_phandle_args *a,
> > +					const struct of_phandle_args *b)
> > +{
> > +	int i;
> > +
> > +	if (a->np != b->np)
> > +		return false;
> > +
> > +	if (a->args_count != b->args_count)
> > +		return false;
> > +
> > +	for (i = 0; i < a->args_count; i++) {
> > +		if (a->args[i] != b->args[i])
> > +			return false;
> > +	}
> > +
> > +	return true;
> > +}
> > +
> > +static int irqmux_find_interrupt_index(struct device *dev, struct device_node *np,
> > +				       const struct of_phandle_args *expected_irq)
> > +{
> > +	struct of_phandle_args out_irq;
> > +	bool is_equal;
> > +	int ret;
> > +	int i;
> > +
> > +	for (i = 0; i < IRQMUX_MAX_IRQS; i++) {
> > +		ret = of_irq_parse_one(np, i, &out_irq);  
> 
> I don't really want more users of this... More below.
> 
> > +		if (ret)
> > +			return ret;
> > +
> > +		is_equal = irqmux_is_phandle_args_equal(expected_irq, &out_irq);
> > +		of_node_put(out_irq.np);
> > +		if (is_equal)
> > +			return i;
> > +	}
> > +
> > +	return -ENOENT;
> > +}
> > +
> > +struct irqmux_cb_data {
> > +	struct device_node *np;
> > +	struct device *dev;
> > +	u32 __iomem *regs;
> > +};
> > +
> > +static int irqmux_imap_cb(void *data, const __be32 *imap,
> > +			  const struct of_phandle_args *parent_args)
> > +{
> > +	struct irqmux_cb_data *priv = data;
> > +	u32 src_hwirq;
> > +	int index;
> > +
> > +	/*
> > +	 * The child #address-cells is 0. Already checked in irqmux_setup().
> > +	 * The first value in imap is the src_hwirq
> > +	 */
> > +	src_hwirq = be32_to_cpu(*imap);  
> 
> The iterator should take care of the endianness conversion.

Ok, it will take care.

> 
> > +
> > +	/*
> > +	 * Get the index in our interrupt array that matches the parent in the
> > +	 * interrupt-map
> > +	 */
> > +	index = irqmux_find_interrupt_index(priv->dev, priv->np, parent_args);
> > +	if (index < 0)
> > +		return dev_err_probe(priv->dev, index, "output interrupt not found\n");
> > +
> > +	dev_info(priv->dev, "interrupt %u mapped to output interrupt[%u]\n",
> > +		 src_hwirq, index);  
> 
> Do you even need "interrupts"? Just make the "interrupt-map" index 
> important and correspond to the hw index. That would greatly simplify 
> all this.

I would like to avoid to be based on the interrupt-map index.

Indeed, IMHO, it is less robust. I don't thing that we can enforce the
interrupt-map items order. Based on interrupt-map index, we need to ensure
that the first item is related to GIC 103, the second one to GIC 104 and so
on.

Anyway, I can simplify the code relying on the interrupt-map index even if
it is less robust.

I will propose this rework in the next iteration.

Best regards,
Hervé


> 
> > +
> > +	/*
> > +	 * Our interrupt array items matches 1:1 the interrupt lines that could
> > +	 * be configured by registers (same order, same number).
> > +	 * Configure the related register with the src hwirq retrieved from the
> > +	 * interrupt-map.
> > +	 */
> > +	writel(src_hwirq, priv->regs + index);
> > +
> > +	return 0;
> > +}  

Re: [PATCH 5/6] soc: renesas: Add support for Renesas RZ/N1 GPIO Interrupt Multiplexer

[Rob Herring]

On Wed, Jul 30, 2025 at 11:54:21AM +0200, Herve Codina wrote:
> Hi Rob,
> 
> On Tue, 29 Jul 2025 14:51:37 -0500
> Rob Herring <robh@kernel.org> wrote:
> 
> > On Fri, Jul 25, 2025 at 05:26:14PM +0200, Herve Codina wrote:
> > > On the Renesas RZ/N1 SoC, GPIOs can generate interruptions. Those
> > > interruption lines are multiplexed by the GPIO Interrupt Multiplexer in
> > > order to map 32 * 3 GPIO interrupt lines to 8 GIC interrupt lines.
> > > 
> > > The GPIO interrupt multiplexer IP does nothing but select 8 GPIO
> > > IRQ lines out of the 96 available to wire them to the GIC input lines.
> > > 
> > > Signed-off-by: Herve Codina <herve.codina@bootlin.com>
> > > ---
> > >  drivers/soc/renesas/Kconfig       |   4 +
> > >  drivers/soc/renesas/Makefile      |   1 +
> > >  drivers/soc/renesas/rzn1_irqmux.c | 169 ++++++++++++++++++++++++++++++
> > >  3 files changed, 174 insertions(+)
> > >  create mode 100644 drivers/soc/renesas/rzn1_irqmux.c
> > > 
> > > diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
> > > index fbc3b69d21a7..9e8ac33052fb 100644
> > > --- a/drivers/soc/renesas/Kconfig
> > > +++ b/drivers/soc/renesas/Kconfig
> > > @@ -58,6 +58,7 @@ config ARCH_RZN1
> > >  	select PM
> > >  	select PM_GENERIC_DOMAINS
> > >  	select ARM_AMBA
> > > +	select RZN1_IRQMUX
> > >  
> > >  if ARM && ARCH_RENESAS
> > >  
> > > @@ -435,6 +436,9 @@ config PWC_RZV2M
> > >  config RST_RCAR
> > >  	bool "Reset Controller support for R-Car" if COMPILE_TEST
> > >  
> > > +config RZN1_IRQMUX
> > > +	bool "Renesas RZ/N1 GPIO IRQ multiplexer support" if COMPILE_TEST
> > > +
> > >  config SYSC_RZ
> > >  	bool "System controller for RZ SoCs" if COMPILE_TEST
> > >  
> > > diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile
> > > index 3bdcc6a395d5..daa932c7698d 100644
> > > --- a/drivers/soc/renesas/Makefile
> > > +++ b/drivers/soc/renesas/Makefile
> > > @@ -14,4 +14,5 @@ obj-$(CONFIG_SYS_R9A09G057)	+= r9a09g057-sys.o
> > >  # Family
> > >  obj-$(CONFIG_PWC_RZV2M)		+= pwc-rzv2m.o
> > >  obj-$(CONFIG_RST_RCAR)		+= rcar-rst.o
> > > +obj-$(CONFIG_RZN1_IRQMUX)		+= rzn1_irqmux.o
> > >  obj-$(CONFIG_SYSC_RZ)		+= rz-sysc.o
> > > diff --git a/drivers/soc/renesas/rzn1_irqmux.c b/drivers/soc/renesas/rzn1_irqmux.c
> > > new file mode 100644
> > > index 000000000000..37e41c2b9104
> > > --- /dev/null
> > > +++ b/drivers/soc/renesas/rzn1_irqmux.c
> > > @@ -0,0 +1,169 @@
> > > +// SPDX-License-Identifier: GPL-2.0-only
> > > +/*
> > > + * RZ/N1 GPIO Interrupt Multiplexer
> > > + *
> > > + * Copyright 2025 Schneider Electric
> > > + * Author: Herve Codina <herve.codina@bootlin.com>
> > > + */
> > > +
> > > +#include <linux/mod_devicetable.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of.h>
> > > +#include <linux/of_irq.h>
> > > +#include <linux/platform_device.h>
> > > +
> > > +#define IRQMUX_MAX_IRQS 8
> > > +
> > > +static int irqmux_is_phandle_args_equal(const struct of_phandle_args *a,
> > > +					const struct of_phandle_args *b)
> > > +{
> > > +	int i;
> > > +
> > > +	if (a->np != b->np)
> > > +		return false;
> > > +
> > > +	if (a->args_count != b->args_count)
> > > +		return false;
> > > +
> > > +	for (i = 0; i < a->args_count; i++) {
> > > +		if (a->args[i] != b->args[i])
> > > +			return false;
> > > +	}
> > > +
> > > +	return true;
> > > +}
> > > +
> > > +static int irqmux_find_interrupt_index(struct device *dev, struct device_node *np,
> > > +				       const struct of_phandle_args *expected_irq)
> > > +{
> > > +	struct of_phandle_args out_irq;
> > > +	bool is_equal;
> > > +	int ret;
> > > +	int i;
> > > +
> > > +	for (i = 0; i < IRQMUX_MAX_IRQS; i++) {
> > > +		ret = of_irq_parse_one(np, i, &out_irq);  
> > 
> > I don't really want more users of this... More below.
> > 
> > > +		if (ret)
> > > +			return ret;
> > > +
> > > +		is_equal = irqmux_is_phandle_args_equal(expected_irq, &out_irq);
> > > +		of_node_put(out_irq.np);
> > > +		if (is_equal)
> > > +			return i;
> > > +	}
> > > +
> > > +	return -ENOENT;
> > > +}
> > > +
> > > +struct irqmux_cb_data {
> > > +	struct device_node *np;
> > > +	struct device *dev;
> > > +	u32 __iomem *regs;
> > > +};
> > > +
> > > +static int irqmux_imap_cb(void *data, const __be32 *imap,
> > > +			  const struct of_phandle_args *parent_args)
> > > +{
> > > +	struct irqmux_cb_data *priv = data;
> > > +	u32 src_hwirq;
> > > +	int index;
> > > +
> > > +	/*
> > > +	 * The child #address-cells is 0. Already checked in irqmux_setup().
> > > +	 * The first value in imap is the src_hwirq
> > > +	 */
> > > +	src_hwirq = be32_to_cpu(*imap);  
> > 
> > The iterator should take care of the endianness conversion.
> 
> Ok, it will take care.
> 
> > 
> > > +
> > > +	/*
> > > +	 * Get the index in our interrupt array that matches the parent in the
> > > +	 * interrupt-map
> > > +	 */
> > > +	index = irqmux_find_interrupt_index(priv->dev, priv->np, parent_args);
> > > +	if (index < 0)
> > > +		return dev_err_probe(priv->dev, index, "output interrupt not found\n");
> > > +
> > > +	dev_info(priv->dev, "interrupt %u mapped to output interrupt[%u]\n",
> > > +		 src_hwirq, index);  
> > 
> > Do you even need "interrupts"? Just make the "interrupt-map" index 
> > important and correspond to the hw index. That would greatly simplify 
> > all this.
> 
> I would like to avoid to be based on the interrupt-map index.
> 
> Indeed, IMHO, it is less robust. I don't thing that we can enforce the
> interrupt-map items order. Based on interrupt-map index, we need to ensure
> that the first item is related to GIC 103, the second one to GIC 104 and so
> on.

How exactly are you enforcing that order for "interrupts"? You can't. 

Aren't you just duplicating the information in "interrupts" in the 
interrupt-map.

Rob

Re: [PATCH 5/6] soc: renesas: Add support for Renesas RZ/N1 GPIO Interrupt Multiplexer

[Herve Codina]

Hi Rob,

On Wed, 30 Jul 2025 15:47:33 -0500
Rob Herring <robh@kernel.org> wrote:

...
> > > > +
> > > > +static int irqmux_imap_cb(void *data, const __be32 *imap,
> > > > +			  const struct of_phandle_args *parent_args)
> > > > +{
> > > > +	struct irqmux_cb_data *priv = data;
> > > > +	u32 src_hwirq;
> > > > +	int index;
> > > > +
> > > > +	/*
> > > > +	 * The child #address-cells is 0. Already checked in irqmux_setup().
> > > > +	 * The first value in imap is the src_hwirq
> > > > +	 */
> > > > +	src_hwirq = be32_to_cpu(*imap);    
> > > 
> > > The iterator should take care of the endianness conversion.  
> > 
> > Ok, it will take care.
> >   
> > >   
> > > > +
> > > > +	/*
> > > > +	 * Get the index in our interrupt array that matches the parent in the
> > > > +	 * interrupt-map
> > > > +	 */
> > > > +	index = irqmux_find_interrupt_index(priv->dev, priv->np, parent_args);
> > > > +	if (index < 0)
> > > > +		return dev_err_probe(priv->dev, index, "output interrupt not found\n");
> > > > +
> > > > +	dev_info(priv->dev, "interrupt %u mapped to output interrupt[%u]\n",
> > > > +		 src_hwirq, index);    
> > > 
> > > Do you even need "interrupts"? Just make the "interrupt-map" index 
> > > important and correspond to the hw index. That would greatly simplify 
> > > all this.  
> > 
> > I would like to avoid to be based on the interrupt-map index.
> > 
> > Indeed, IMHO, it is less robust. I don't thing that we can enforce the
> > interrupt-map items order. Based on interrupt-map index, we need to ensure
> > that the first item is related to GIC 103, the second one to GIC 104 and so
> > on.  
> 
> How exactly are you enforcing that order for "interrupts"? You can't.

I can impose interrupt-names property in the binding and at least, those
names are to be in order (checked by dtbs_check).

Based on that if a mismatch is present between interrupt-names and
interrupts it is an issue in the dts used.

With interrupt-map, nothing can be imposed and so nothing can be checked.

> 
> Aren't you just duplicating the information in "interrupts" in the 
> interrupt-map.
> 

I will remove 'interrupts' in the next iteration and use only 'interrupt-map'.

I will add some information related to the order of the interrup-map item in the
binding (description of the interrupt-map property).

Best regards,
Hervé

Re: [PATCH 0/6] gpio: renesas: Add support for GPIO and related interrupts in RZ/N1 SoC

[Wolfram Sang]

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Hi Herve,

> 			drive-strength = <6>;
> 			bias-disable;

So, I missed those but sadly it didn't make a difference.

> 
> I have checked /sys/kernel/debug/pinctrl/40067000.pinctrl/pinmux-pins and
> I have also the "(GPIO UNCLAIMED)":

Still looks wrong. But is unrelated to my problem.

> When you described the LED on your side, did you reference the GPIO using &gpio1b
> for instance gpios = <&gpio1b 23 GPIO_ACTIVE_HIGH>;

Yes.

> For GPIO accesses from user space I used gpioget/gpioset tools from libgpiod
> without any issues to read/write a GPIO.

I use the sysfs interface. Also tried without the LED subsystem by
directly using the GPIO sysfs interface. The 'gpio' file in debugfs
reflects my changes, alas the LED does not glow :(

I tried a little bit here and there to no avail. I also tried to build
the BSP kernel to see if the LEDs light up there. Couldn't get that
kernel to boot even.

Conclusion: My gut feeling tells me that your patches are okay and I am
doing something stupidly wrong. But I need to tackle this with focus and
not as a side-task. Sadly, I can't do this before my holidays (starting
tomorrow), so I can only do this at the end of this month. I will make
this a priority thing for 6.18, though. Finally GPIO on this SoC would
be awesome and allows me to enable way more devices on my board.

Sorry for no better news...

All the best,

   Wolfram


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