[PATCH 0/2] RZ/G2L pinctrl improvements

[PATCH 0/2] RZ/G2L pinctrl improvements

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

The write to PFC_OEN register is controlled by the write protect register
(PWPR). Currently we are setting OEN register in resume() without enabling
the write access in PWPR leading to incorrect operation.

Also don't reconfigure the pin if the pin's configuration values are same
as reset values during resume() to avoid spurious IRQ.

Logs:
root@smarc-rzg3e:~# cat /proc/interrupts | grep SLEEP
127:          0          0          0          0 rzv2h-icu   0 Edge      SLEEP
root@smarc-rzg3e:~# [   68.710624] PM: suspend entry (deep)
[   68.714523] Filesystems sync: 0.000 seconds
[   68.720402] Freezing user space processes
[   68.726527] Freezing user space processes completed (elapsed 0.001 seconds)
[   68.733563] OOM killer disabled.
[   68.736839] Freezing remaining freezable tasks
[   68.742749] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
[   68.750233] printk: Suspending console(s) (use no_console_suspend to debug)
NOTICE:  BL2: v2.10.5(release):2.10.5/rz_soc_dev-169-g1410189b0
NOTICE:  BL2: Built : 12:53:12, Jul 15 2025
NOTICE:  BL2: SYS_LSI_MODE: 0x13e06
NOTICE:  BL2: SYS_LSI_DEVID: 0x8679447
NOTICE:  BL2: SYS_LSI_PRR: 0x0
NOTICE:  BL2: Booting BL31
[   68.800343] renesas-gbeth 15c30000.ethernet end0: Link is Down
[   68.812953] Disabling non-boot CPUs ...
[   68.817380] psci: CPU3 killed (polled 0 ms)
[   68.823030] psci: CPU2 killed (polled 4 ms)
[   68.829144] psci: CPU1 killed (polled 0 ms)
[   68.833581] Enabling non-boot CPUs ...
[   68.833789] Detected VIPT I-cache on CPU1
[   68.833836] GICv3: CPU1: found redistributor 100 region 0:0x0000000014960000
[   68.833875] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
[   68.834651] CPU1 is up
[   68.834748] Detected VIPT I-cache on CPU2
[   68.834770] GICv3: CPU2: found redistributor 200 region 0:0x0000000014980000
[   68.834790] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
[   68.835438] CPU2 is up
[   68.835533] Detected VIPT I-cache on CPU3
[   68.835555] GICv3: CPU3: found redistributor 300 region 0:0x00000000149a0000
[   68.835576] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
[   68.836210] CPU3 is up
[   68.862815] dwmac4: Master AXI performs fixed burst length
[   68.863715] renesas-gbeth 15c30000.ethernet end0: No Safety Features support found
[   68.863736] renesas-gbeth 15c30000.ethernet end0: IEEE 1588-2008 Advanced Timestamp supported
[   68.867251] renesas-gbeth 15c30000.ethernet end0: configuring for phy/rgmii-id link mode
[   68.882826] dwmac4: Master AXI performs fixed burst length
[   68.883716] renesas-gbeth 15c40000.ethernet end1: No Safety Features support found
[   68.883731] renesas-gbeth 15c40000.ethernet end1: IEEE 1588-2008 Advanced Timestamp supported
[   68.887264] renesas-gbeth 15c40000.ethernet end1: configuring for phy/rgmii-id link mode
[   69.083883] OOM killer enabled.
[   69.087021] Restarting tasks: Starting
[   69.091764] Restarting tasks: Done
[   69.095229] random: crng reseeded on system resumption
[   69.100457] PM: suspend exit
[   71.436765] renesas-gbeth 15c30000.ethernet end0: Link is Up - 1Gbps/Full - flow control rx/tx
[   72.868712] Process accounting resumed

root@smarc-rzg3e:~# cat /proc/interrupts | grep SLEEP
127:          1          0          0          0 rzv2h-icu   0 Edge      SLEEP
root@smarc-rzg3e:~#

Biju Das (2):
  pinctrl: renesas: rzg2l: Fix OEN resume
  pinctrl: renesas: rzg2l: Don't reconfigure the pin if it is same as
    reset values

 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 44 +++++++++++++++++--------
 1 file changed, 31 insertions(+), 13 deletions(-)

-- 
2.43.0

[PATCH 1/2] pinctrl: renesas: rzg2l: Fix OEN resume

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

The write to PFC_OEN register is controlled by the write protect register
(PWPR). Currently we are setting OEN register in resume() without enabling
the write access in PWPR leading to incorrect operation.

Fixes: cd39805be85b ("pinctrl: renesas: rzg2l: Unify OEN handling across RZ/{G2L,V2H,V2N}")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index b182b3b8a542..2b5d16594bb7 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -3165,6 +3165,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
 	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
 	const struct rzg2l_register_offsets *regs = &hwcfg->regs;
 	struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
+	unsigned long flags;
+	u8 pwpr;
 	int ret;
 
 	if (!atomic_read(&pctrl->wakeup_path)) {
@@ -3174,7 +3176,15 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)
 	}
 
 	writeb(cache->qspi, pctrl->base + QSPI);
+	spin_lock_irqsave(&pctrl->lock, flags);
+	if (pctrl->data->hwcfg->oen_pwpr_lock) {
+		pwpr = readb(pctrl->base + regs->pwpr);
+		writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr);
+	}
 	writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen);
+	if (pctrl->data->hwcfg->oen_pwpr_lock)
+		writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr);
+	spin_unlock_irqrestore(&pctrl->lock, flags);
 	for (u8 i = 0; i < 2; i++) {
 		if (regs->sd_ch)
 			writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));
-- 
2.43.0

[PATCH 2/2] pinctrl: renesas: rzg2l: Don't reconfigure the pin if it is same as reset values

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Don't reconfigure the pin if the pin's configuration values are same as
reset values during resume() to avoid spurious IRQ. E.g: For NMI function
the PS0 pin configuration are PMC = 1 and PFC = 0 and is same as that of
reset values. Currently during resume the pin is already in NMI function.
But the code is forcefully setting it to GPIO HI-Z state and then again
reconfiguring to NMI function leading to spurious IRQ.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 34 +++++++++++++++----------
 1 file changed, 21 insertions(+), 13 deletions(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 2b5d16594bb7..086fcb18c6d8 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -3103,27 +3103,35 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
 		pm = readw(pctrl->base + PM(off));
 		for_each_set_bit(pin, &pinmap, max_pin) {
 			struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
+			u32 pfc_mask;
+			u32 pfc_val;
 
 			/* Nothing to do if PFC was not configured before. */
 			if (!(cache->pmc[port] & BIT(pin)))
 				continue;
 
-			/* Set pin to 'Non-use (Hi-Z input protection)' */
-			pm &= ~(PM_MASK << (pin * 2));
-			writew(pm, pctrl->base + PM(off));
+			pfc_val = readl(pctrl->base + PFC(off));
+			pfc_mask = PFC_MASK << (pin * 4);
 
-			/* Temporarily switch to GPIO mode with PMC register */
-			pmc &= ~BIT(pin);
-			writeb(pmc, pctrl->base + PMC(off));
+			/* Nothing to do if reset value of the pin is same as cached value */
+			if ((cache->pfc[port] & pfc_mask) != (pfc_val & pfc_mask)) {
+				/* Set pin to 'Non-use (Hi-Z input protection)' */
+				pm &= ~(PM_MASK << (pin * 2));
+				writew(pm, pctrl->base + PM(off));
 
-			/* Select Pin function mode. */
-			pfc &= ~(PFC_MASK << (pin * 4));
-			pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4)));
-			writel(pfc, pctrl->base + PFC(off));
+				/* Temporarily switch to GPIO mode with PMC register */
+				pmc &= ~BIT(pin);
+				writeb(pmc, pctrl->base + PMC(off));
 
-			/* Switch to Peripheral pin function. */
-			pmc |= BIT(pin);
-			writeb(pmc, pctrl->base + PMC(off));
+				/* Select Pin function mode. */
+				pfc &= ~pfc_mask;
+				pfc |= cache->pfc[port] & pfc_mask;
+				writel(pfc, pctrl->base + PFC(off));
+
+				/* Switch to Peripheral pin function. */
+				pmc |= BIT(pin);
+				writeb(pmc, pctrl->base + PMC(off));
+			}
 		}
 	}
 
-- 
2.43.0

RE: [PATCH 2/2] pinctrl: renesas: rzg2l: Don't reconfigure the pin if it is same as reset values

[Biju Das]

Hi All,

> -----Original Message-----
> From: Biju <biju.das.au@gmail.com>
> Sent: 15 August 2025 15:48
> Subject: [PATCH 2/2] pinctrl: renesas: rzg2l: Don't reconfigure the pin if it is same as reset values
> 
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Don't reconfigure the pin if the pin's configuration values are same as reset values during resume() to
> avoid spurious IRQ. E.g: For NMI function the PS0 pin configuration are PMC = 1 and PFC = 0 and is same
> as that of reset values. Currently during resume the pin is already in NMI function.
> But the code is forcefully setting it to GPIO HI-Z state and then again reconfiguring to NMI function
> leading to spurious IRQ.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  drivers/pinctrl/renesas/pinctrl-rzg2l.c | 34 +++++++++++++++----------
>  1 file changed, 21 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index 2b5d16594bb7..086fcb18c6d8 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -3103,27 +3103,35 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
>  		pm = readw(pctrl->base + PM(off));
>  		for_each_set_bit(pin, &pinmap, max_pin) {
>  			struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
> +			u32 pfc_mask;
> +			u32 pfc_val;
> 
>  			/* Nothing to do if PFC was not configured before. */
>  			if (!(cache->pmc[port] & BIT(pin)))
>  				continue;
> 
> -			/* Set pin to 'Non-use (Hi-Z input protection)' */
> -			pm &= ~(PM_MASK << (pin * 2));
> -			writew(pm, pctrl->base + PM(off));
> +			pfc_val = readl(pctrl->base + PFC(off));
> +			pfc_mask = PFC_MASK << (pin * 4);
> 
> -			/* Temporarily switch to GPIO mode with PMC register */
> -			pmc &= ~BIT(pin);
> -			writeb(pmc, pctrl->base + PMC(off));
> +			/* Nothing to do if reset value of the pin is same as cached value */
> +			if ((cache->pfc[port] & pfc_mask) != (pfc_val & pfc_mask)) {
> +				/* Set pin to 'Non-use (Hi-Z input protection)' */
> +				pm &= ~(PM_MASK << (pin * 2));
> +				writew(pm, pctrl->base + PM(off));
> 
> -			/* Select Pin function mode. */
> -			pfc &= ~(PFC_MASK << (pin * 4));
> -			pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4)));
> -			writel(pfc, pctrl->base + PFC(off));
> +				/* Temporarily switch to GPIO mode with PMC register */
> +				pmc &= ~BIT(pin);
> +				writeb(pmc, pctrl->base + PMC(off));
> 
> -			/* Switch to Peripheral pin function. */
> -			pmc |= BIT(pin);
> -			writeb(pmc, pctrl->base + PMC(off));
> +				/* Select Pin function mode. */
> +				pfc &= ~pfc_mask;
> +				pfc |= cache->pfc[port] & pfc_mask;
> +				writel(pfc, pctrl->base + PFC(off));
> +
> +				/* Switch to Peripheral pin function. */
> +				pmc |= BIT(pin);
> +				writeb(pmc, pctrl->base + PMC(off));
> +			}

I will send v2, as I forgot to update rzg2l_pinctrl_set_pfc_mode()
Aswell.

Cheers,
Biju



>  		}
>  	}
> 
> --
> 2.43.0